Merge pull request #1437 from freechipsproject/name-conflicts

Check for name collisions of Modules

1 files changed, 43 insertions, 0 deletions

diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala
index 9a384d21..aa154bab 100644
--- a/src/test/scala/firrtlTests/CheckSpec.scala
+++ b/src/test/scala/firrtlTests/CheckSpec.scala
@@ -307,6 +307,49 @@ class CheckSpec extends FlatSpec with Matchers {
       }
     }
   }
+
+  s"Duplicate module names" should "throw an exception" in {
+    val input =
+      s"""|circuit bar :
+          |  module bar :
+          |    input i : UInt<8>
+          |    output o : UInt<8>
+          |    o <= i
+          |  module dup :
+          |    input i : UInt<8>
+          |    output o : UInt<8>
+          |    o <= i
+          |  module dup :
+          |    input i : UInt<8>
+          |    output o : UInt<8>
+          |    o <= not(i)
+          |""".stripMargin
+    assertThrows[CheckHighForm.ModuleNameNotUniqueException] {
+      try {
+        checkHighInput(input)
+      } catch {
+        case e: firrtl.passes.PassExceptions => throw e.exceptions.head
+      }
+    }
+  }
+
+  s"Defnames that conflict with pure-FIRRTL module names" should "throw an exception" in {
+    val input =
+      s"""|circuit bar :
+          |  module bar :
+          |    input i : UInt<8>
+          |    output o : UInt<8>
+          |    o <= i
+          |  extmodule dup :
+          |    input i : UInt<8>
+          |    output o : UInt<8>
+          |    defname = bar
+          |""".stripMargin
+    assertThrows[CheckHighForm.DefnameConflictException] {
+      checkHighInput(input)
+    }
+  }
+
 }
 
 object CheckSpec {