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authorchick2019-08-01 09:21:52 -0700
committerchick2019-08-01 10:52:22 -0700
commit54e67889f10b39323fb729808b8cd22b4c832910 (patch)
tree4b5916fe8e6cee619ab5dfc3549bfb625b5b8214 /src/test/scala/firrtlTests/transforms
parent86d2470d8294a4dba37d33ba021558ba33da4d65 (diff)
Followup to PR #1142
Fixes a threading bug in where lazy reading of file caused a problem for multithreaded access to the that was read. Changes all uses of io.Source to use new API getText getLines getTextResource getLinesResouce Make style to only import FileUtils and not its methods So code is more explicit as e.g. FileUtils.getText()
Diffstat (limited to 'src/test/scala/firrtlTests/transforms')
-rw-r--r--src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala5
-rw-r--r--src/test/scala/firrtlTests/transforms/TopWiringTest.scala1
2 files changed, 2 insertions, 4 deletions
diff --git a/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala b/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
index 089e837a..6e63317b 100644
--- a/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
@@ -6,6 +6,7 @@ import firrtl.annotations.{Annotation, CircuitName, ModuleName}
import firrtl.transforms._
import firrtl.{FIRRTLException, Transform, VerilogCompiler, VerilogEmitter}
import firrtlTests.{HighTransformSpec, LowTransformSpec}
+import firrtl.FileUtils
import org.scalacheck.Test.Failed
import org.scalatest.{FreeSpec, Matchers, Succeeded}
@@ -132,9 +133,7 @@ class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec {
// but our file list should not include the verilog header file.
val fileListFile = new java.io.File(s"test_run_dir/${BlackBoxSourceHelper.defaultFileListName}")
fileListFile.exists should be (true)
- val fileListFileSource = io.Source.fromFile(fileListFile)
- val fileList = fileListFileSource.getLines.mkString
- fileListFileSource.close()
+ val fileList = FileUtils.getText(fileListFile)
fileList.contains("ParameterizedViaHeaderAdderExtModule.v") should be (true)
fileList.contains("VerilogHeaderFile.vh") should be (false)
}
diff --git a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
index 16dffd66..9dd290f8 100644
--- a/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
+++ b/src/test/scala/firrtlTests/transforms/TopWiringTest.scala
@@ -6,7 +6,6 @@ package transforms
import org.scalatest.FlatSpec
import org.scalatest.Matchers
import org.scalatest.junit.JUnitRunner
-import scala.io.Source
import java.io._
import firrtl._