All of src/ formatted with scalafmt

1 files changed, 9 insertions, 9 deletions

diff --git a/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala b/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala
index f57586f6..6ee0f5a0 100644
--- a/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala
+++ b/src/test/scala/firrtlTests/transforms/LegalizeClocks.scala
@@ -10,7 +10,7 @@ class LegalizeClocksTransformSpec extends FirrtlFlatSpec {
   def compile(input: String): CircuitState =
     (new MinimumVerilogCompiler).compileAndEmit(CircuitState(parse(input), ChirrtlForm), Nil)
 
-  behavior of "LegalizeClocksTransform"
+  behavior.of("LegalizeClocksTransform")
 
   it should "not emit @(posedge 1'h0) for stop" in {
     val input =
@@ -19,8 +19,8 @@ class LegalizeClocksTransformSpec extends FirrtlFlatSpec {
         |    stop(asClock(UInt(1)), UInt(1), 1)
         |""".stripMargin
     val result = compile(input)
-    result should containLine (s"always @(posedge _GEN_0) begin")
-    result.getEmittedCircuit.value shouldNot include ("always @(posedge 1")
+    result should containLine(s"always @(posedge _GEN_0) begin")
+    result.getEmittedCircuit.value shouldNot include("always @(posedge 1")
   }
 
   it should "not emit @(posedge 1'h0) for printf" in {
@@ -30,8 +30,8 @@ class LegalizeClocksTransformSpec extends FirrtlFlatSpec {
         |    printf(asClock(UInt(1)), UInt(1), "hi")
         |""".stripMargin
     val result = compile(input)
-    result should containLine (s"always @(posedge _GEN_0) begin")
-    result.getEmittedCircuit.value shouldNot include ("always @(posedge 1")
+    result should containLine(s"always @(posedge _GEN_0) begin")
+    result.getEmittedCircuit.value shouldNot include("always @(posedge 1")
   }
 
   it should "not emit @(posedge 1'h0) for reg" in {
@@ -45,8 +45,8 @@ class LegalizeClocksTransformSpec extends FirrtlFlatSpec {
         |    out <= r
         |""".stripMargin
     val result = compile(input)
-    result should containLine (s"always @(posedge _GEN_0) begin")
-    result.getEmittedCircuit.value shouldNot include ("always @(posedge 1")
+    result should containLine(s"always @(posedge _GEN_0) begin")
+    result.getEmittedCircuit.value shouldNot include("always @(posedge 1")
   }
 
   it should "deduplicate injected nodes for literal clocks" in {
@@ -57,11 +57,11 @@ class LegalizeClocksTransformSpec extends FirrtlFlatSpec {
         |    stop(asClock(UInt(1)), UInt(1), 1)
         |""".stripMargin
     val result = compile(input)
-    result should containLine (s"wire  _GEN_0 = 1'h1;")
+    result should containLine(s"wire  _GEN_0 = 1'h1;")
     // Check that there's only 1 _GEN_0 instantiation
     val verilog = result.getEmittedCircuit.value
     val matches = "wire\\s+_GEN_0\\s+=\\s+1'h1".r.findAllIn(verilog)
-    matches.size should be (1)
+    matches.size should be(1)
 
   }
 }