GroupModule Transform (#766)

* Added grouping pass

* Added InfoMagnet and infomappers

* Changed return type of execute to allow final CircuitState inspection

* Updated dedup. Now is name-agnostic

* Added GroupAndDedup transform

1 files changed, 198 insertions, 138 deletions

diff --git a/src/test/scala/firrtlTests/transforms/DedupTests.scala b/src/test/scala/firrtlTests/transforms/DedupTests.scala
index e88bd506..6fab902e 100644
--- a/src/test/scala/firrtlTests/transforms/DedupTests.scala
+++ b/src/test/scala/firrtlTests/transforms/DedupTests.scala
@@ -3,150 +3,210 @@
 package firrtlTests
 package transform
 
-import org.scalatest.FlatSpec
-import org.scalatest.Matchers
-import org.scalatest.junit.JUnitRunner
-
-import firrtl.ir.Circuit
-import firrtl.Parser
-import firrtl.passes.PassExceptions
-import firrtl.annotations.{
-   Named,
-   CircuitName,
-   ModuleName,
-   Annotation
-}
-import firrtl.transforms.{DedupModules, NoDedupAnnotation}
+import firrtl.annotations._
+import firrtl.transforms.{DedupModules}
 
 
 /**
  * Tests inline instances transformation
  */
 class DedupModuleTests extends HighTransformSpec {
-   def transform = new DedupModules
-   "The module A" should "be deduped" in {
-      val input =
-         """circuit Top :
-           |  module Top :
-           |    inst a1 of A
-           |    inst a2 of A_
-           |  module A :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |  module A_ :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           """.stripMargin
-      val check =
-         """circuit Top :
-           |  module Top :
-           |    inst a1 of A
-           |    inst a2 of A
-           |  module A :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           """.stripMargin
-      execute(input, check, Seq.empty)
-   }
-   "The module A and B" should "be deduped" in {
-      val input =
-         """circuit Top :
-           |  module Top :
-           |    inst a1 of A
-           |    inst a2 of A_
-           |  module A :
-           |    output x: UInt<1>
-           |    inst b of B
-           |    x <= b.x
-           |  module A_ :
-           |    output x: UInt<1>
-           |    inst b of B_
-           |    x <= b.x
-           |  module B :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |  module B_ :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           """.stripMargin
-      val check =
-         """circuit Top :
-           |  module Top :
-           |    inst a1 of A
-           |    inst a2 of A
-           |  module A :
-           |    output x: UInt<1>
-           |    inst b of B
-           |    x <= b.x
-           |  module B :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           """.stripMargin
-      execute(input, check, Seq.empty)
-   }
-   "The module A and B with comments" should "be deduped" in {
-      val input =
-         """circuit Top :
-           |  module Top :
-           |    inst a1 of A
-           |    inst a2 of A_
-           |  module A : @[yy 2:2]
-           |    output x: UInt<1> @[yy 2:2]
-           |    inst b of B @[yy 2:2]
-           |    x <= b.x @[yy 2:2]
-           |  module A_ : @[xx 1:1]
-           |    output x: UInt<1> @[xx 1:1]
-           |    inst b of B_ @[xx 1:1]
-           |    x <= b.x @[xx 1:1]
-           |  module B :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           |  module B_ :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           """.stripMargin
-      val check =
-         """circuit Top :
-           |  module Top :
-           |    inst a1 of A
-           |    inst a2 of A
-           |  module A : @[yy 2:2]
-           |    output x: UInt<1> @[yy 2:2]
-           |    inst b of B @[yy 2:2]
-           |    x <= b.x @[yy 2:2]
-           |  module B :
-           |    output x: UInt<1>
-           |    x <= UInt(1)
-           """.stripMargin
-      execute(input, check, Seq.empty)
-   }
-   "The module B, but not A, with comments" should "be deduped if not annotated" in {
-      val input =
-         """circuit Top :
-           |  module Top :
-           |    inst a1 of A
-           |    inst a2 of A_
-           |  module A : @[yy 2:2]
-           |    output x: UInt<1> @[yy 2:2]
-           |    x <= UInt(1)
-           |  module A_ : @[xx 1:1]
-           |    output x: UInt<1> @[xx 1:1]
-           |    x <= UInt(1)
-           """.stripMargin
-      val check =
-         """circuit Top :
-           |  module Top :
-           |    inst a1 of A
-           |    inst a2 of A_
-           |  module A : @[yy 2:2]
-           |    output x: UInt<1> @[yy 2:2]
-           |    x <= UInt(1)
-           |  module A_ : @[xx 1:1]
-           |    output x: UInt<1> @[xx 1:1]
-           |    x <= UInt(1)
-           """.stripMargin
-      execute(input, check, Seq(dontDedup("A")))
-   }
+  def transform = new DedupModules
+  "The module A" should "be deduped" in {
+     val input =
+        """circuit Top :
+          |  module Top :
+          |    inst a1 of A
+          |    inst a2 of A_
+          |  module A :
+          |    output x: UInt<1>
+          |    x <= UInt(1)
+          |  module A_ :
+          |    output x: UInt<1>
+          |    x <= UInt(1)
+          """.stripMargin
+     val check =
+        """circuit Top :
+          |  module Top :
+          |    inst a1 of A
+          |    inst a2 of A
+          |  module A :
+          |    output x: UInt<1>
+          |    x <= UInt(1)
+          """.stripMargin
+     execute(input, check, Seq.empty)
+  }
+  "The module A and B" should "be deduped" in {
+     val input =
+        """circuit Top :
+          |  module Top :
+          |    inst a1 of A
+          |    inst a2 of A_
+          |  module A :
+          |    output x: UInt<1>
+          |    inst b of B
+          |    x <= b.x
+          |  module A_ :
+          |    output x: UInt<1>
+          |    inst b of B_
+          |    x <= b.x
+          |  module B :
+          |    output x: UInt<1>
+          |    x <= UInt(1)
+          |  module B_ :
+          |    output x: UInt<1>
+          |    x <= UInt(1)
+          """.stripMargin
+     val check =
+        """circuit Top :
+          |  module Top :
+          |    inst a1 of A
+          |    inst a2 of A
+          |  module A :
+          |    output x: UInt<1>
+          |    inst b of B
+          |    x <= b.x
+          |  module B :
+          |    output x: UInt<1>
+          |    x <= UInt(1)
+          """.stripMargin
+     execute(input, check, Seq.empty)
+  }
+  "The module A and B with comments" should "be deduped" in {
+     val input =
+        """circuit Top :
+          |  module Top :
+          |    inst a1 of A
+          |    inst a2 of A_
+          |  module A : @[yy 2:2]
+          |    output x: UInt<1> @[yy 2:2]
+          |    inst b of B @[yy 2:2]
+          |    x <= b.x @[yy 2:2]
+          |  module A_ : @[xx 1:1]
+          |    output x: UInt<1> @[xx 1:1]
+          |    inst b of B_ @[xx 1:1]
+          |    x <= b.x @[xx 1:1]
+          |  module B :
+          |    output x: UInt<1>
+          |    x <= UInt(1)
+          |  module B_ :
+          |    output x: UInt<1>
+          |    x <= UInt(1)
+          """.stripMargin
+     val check =
+        """circuit Top :
+          |  module Top :
+          |    inst a1 of A
+          |    inst a2 of A
+          |  module A : @[yy 2:2]
+          |    output x: UInt<1> @[yy 2:2]
+          |    inst b of B @[yy 2:2]
+          |    x <= b.x @[yy 2:2]
+          |  module B :
+          |    output x: UInt<1>
+          |    x <= UInt(1)
+          """.stripMargin
+     execute(input, check, Seq.empty)
+  }
+  "A_ but not A" should "be deduped if not annotated" in {
+     val input =
+        """circuit Top :
+          |  module Top :
+          |    inst a1 of A
+          |    inst a2 of A_
+          |  module A : @[yy 2:2]
+          |    output x: UInt<1> @[yy 2:2]
+          |    x <= UInt(1)
+          |  module A_ : @[xx 1:1]
+          |    output x: UInt<1> @[xx 1:1]
+          |    x <= UInt(1)
+          """.stripMargin
+     val check =
+        """circuit Top :
+          |  module Top :
+          |    inst a1 of A
+          |    inst a2 of A_
+          |  module A : @[yy 2:2]
+          |    output x: UInt<1> @[yy 2:2]
+          |    x <= UInt(1)
+          |  module A_ : @[xx 1:1]
+          |    output x: UInt<1> @[xx 1:1]
+          |    x <= UInt(1)
+          """.stripMargin
+     execute(input, check, Seq(dontDedup("A")))
+  }
+  "The module A and A_" should "be deduped even with different port names and info, and annotations should remap" in {
+     val input =
+        """circuit Top :
+          |  module Top :
+          |    output out: UInt<1>
+          |    inst a1 of A
+          |    inst a2 of A_
+          |    out <= and(a1.x, a2.y)
+          |  module A : @[yy 2:2]
+          |    output x: UInt<1> @[yy 2:2]
+          |    x <= UInt(1)
+          |  module A_ : @[xx 1:1]
+          |    output y: UInt<1> @[xx 1:1]
+          |    y <= UInt(1)
+        """.stripMargin
+     val check =
+        """circuit Top :
+          |  module Top :
+          |    output out: UInt<1>
+          |    inst a1 of A
+          |    inst a2 of A
+          |    out <= and(a1.x, a2.x)
+          |  module A : @[yy 2:2]
+          |    output x: UInt<1> @[yy 2:2]
+          |    x <= UInt(1)
+        """.stripMargin
+     case class DummyAnnotation(target: ComponentName) extends SingleTargetAnnotation[ComponentName] {
+       override def duplicate(n: ComponentName): Annotation = DummyAnnotation(n)
+     }
+
+     val mname = ModuleName("Top", CircuitName("Top"))
+     val finalState = execute(input, check, Seq(DummyAnnotation(ComponentName("a2.y", mname))))
+
+     finalState.annotations.collect({ case d: DummyAnnotation => d }).head should be(DummyAnnotation(ComponentName("a2.x", mname)))
+
+  }
+  "The module A and B" should "be deduped with the first module in order" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A_
+        |  module A :
+        |    output x: UInt<1>
+        |    inst b of B_
+        |    x <= b.x
+        |  module A_ :
+        |    output x: UInt<1>
+        |    inst b of B
+        |    x <= b.x
+        |  module B :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |  module B_ :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+      """.stripMargin
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A
+        |  module A :
+        |    output x: UInt<1>
+        |    inst b of B
+        |    x <= b.x
+        |  module B :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+      """.stripMargin
+    execute(input, check, Seq.empty)
+  }
 }
 
 // Execution driven tests for inlining modules