All of src/ formatted with scalafmt

1 files changed, 338 insertions, 284 deletions

diff --git a/src/test/scala/firrtlTests/transforms/DedupTests.scala b/src/test/scala/firrtlTests/transforms/DedupTests.scala
index 8ab3026c..8c2835dd 100644
--- a/src/test/scala/firrtlTests/transforms/DedupTests.scala
+++ b/src/test/scala/firrtlTests/transforms/DedupTests.scala
@@ -10,8 +10,8 @@ import firrtl.transforms.{DedupModules, NoCircuitDedupAnnotation}
 import firrtl.testutils._
 
 /**
- * Tests inline instances transformation
- */
+  * Tests inline instances transformation
+  */
 class DedupModuleTests extends HighTransformSpec {
   case class MultiTargetDummyAnnotation(targets: Seq[Target], tag: Int) extends Annotation {
     override def update(renames: RenameMap): Seq[Annotation] = {
@@ -24,234 +24,236 @@ class DedupModuleTests extends HighTransformSpec {
   }
   def transform = new DedupModules
   "The module A" should "be deduped" in {
-     val input =
-        """circuit Top :
-          |  module Top :
-          |    inst a1 of A
-          |    inst a2 of A_
-          |  module A :
-          |    output x: UInt<1>
-          |    x <= UInt(1)
-          |  module A_ :
-          |    output x: UInt<1>
-          |    x <= UInt(1)
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A_
+        |  module A :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |  module A_ :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
           """.stripMargin
-     val check =
-        """circuit Top :
-          |  module Top :
-          |    inst a1 of A
-          |    inst a2 of A
-          |  module A :
-          |    output x: UInt<1>
-          |    x <= UInt(1)
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A
+        |  module A :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
           """.stripMargin
-     execute(input, check, Seq.empty)
+    execute(input, check, Seq.empty)
   }
   "The module A and B" should "be deduped" in {
-     val input =
-        """circuit Top :
-          |  module Top :
-          |    inst a1 of A
-          |    inst a2 of A_
-          |  module A :
-          |    output x: UInt<1>
-          |    inst b of B
-          |    x <= b.x
-          |  module A_ :
-          |    output x: UInt<1>
-          |    inst b of B_
-          |    x <= b.x
-          |  module B :
-          |    output x: UInt<1>
-          |    x <= UInt(1)
-          |  module B_ :
-          |    output x: UInt<1>
-          |    x <= UInt(1)
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A_
+        |  module A :
+        |    output x: UInt<1>
+        |    inst b of B
+        |    x <= b.x
+        |  module A_ :
+        |    output x: UInt<1>
+        |    inst b of B_
+        |    x <= b.x
+        |  module B :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |  module B_ :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
           """.stripMargin
-     val check =
-        """circuit Top :
-          |  module Top :
-          |    inst a1 of A
-          |    inst a2 of A
-          |  module A :
-          |    output x: UInt<1>
-          |    inst b of B
-          |    x <= b.x
-          |  module B :
-          |    output x: UInt<1>
-          |    x <= UInt(1)
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A
+        |  module A :
+        |    output x: UInt<1>
+        |    inst b of B
+        |    x <= b.x
+        |  module B :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
           """.stripMargin
-     execute(input, check, Seq.empty)
+    execute(input, check, Seq.empty)
   }
   "The module A and B with comments" should "be deduped" in {
-     val input =
-        """circuit Top :
-          |  module Top :
-          |    inst a1 of A
-          |    inst a2 of A_
-          |  module A : @[yy 2:2]
-          |    output x: UInt<1> @[yy 2:2]
-          |    inst b of B @[yy 2:2]
-          |    x <= b.x @[yy 2:2]
-          |  module A_ : @[xx 1:1]
-          |    output x: UInt<1> @[xx 1:1]
-          |    inst b of B_ @[xx 1:1]
-          |    x <= b.x @[xx 1:1]
-          |  module B :
-          |    output x: UInt<1>
-          |    x <= UInt(1)
-          |  module B_ :
-          |    output x: UInt<1>
-          |    x <= UInt(1)
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A_
+        |  module A : @[yy 2:2]
+        |    output x: UInt<1> @[yy 2:2]
+        |    inst b of B @[yy 2:2]
+        |    x <= b.x @[yy 2:2]
+        |  module A_ : @[xx 1:1]
+        |    output x: UInt<1> @[xx 1:1]
+        |    inst b of B_ @[xx 1:1]
+        |    x <= b.x @[xx 1:1]
+        |  module B :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
+        |  module B_ :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
           """.stripMargin
-     val check =
-        """circuit Top :
-          |  module Top :
-          |    inst a1 of A
-          |    inst a2 of A
-          |  module A : @[yy 2:2]
-          |    output x: UInt<1> @[yy 2:2]
-          |    inst b of B @[yy 2:2]
-          |    x <= b.x @[yy 2:2]
-          |  module B :
-          |    output x: UInt<1>
-          |    x <= UInt(1)
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A
+        |  module A : @[yy 2:2]
+        |    output x: UInt<1> @[yy 2:2]
+        |    inst b of B @[yy 2:2]
+        |    x <= b.x @[yy 2:2]
+        |  module B :
+        |    output x: UInt<1>
+        |    x <= UInt(1)
           """.stripMargin
-     execute(input, check, Seq.empty)
+    execute(input, check, Seq.empty)
   }
   "A_ but not A" should "be deduped if not annotated" in {
-     val input =
-        """circuit Top :
-          |  module Top :
-          |    inst a1 of A
-          |    inst a2 of A_
-          |  module A : @[yy 2:2]
-          |    output x: UInt<1> @[yy 2:2]
-          |    x <= UInt(1)
-          |  module A_ : @[xx 1:1]
-          |    output x: UInt<1> @[xx 1:1]
-          |    x <= UInt(1)
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A_
+        |  module A : @[yy 2:2]
+        |    output x: UInt<1> @[yy 2:2]
+        |    x <= UInt(1)
+        |  module A_ : @[xx 1:1]
+        |    output x: UInt<1> @[xx 1:1]
+        |    x <= UInt(1)
           """.stripMargin
-     val check =
-        """circuit Top :
-          |  module Top :
-          |    inst a1 of A
-          |    inst a2 of A_
-          |  module A : @[yy 2:2]
-          |    output x: UInt<1> @[yy 2:2]
-          |    x <= UInt(1)
-          |  module A_ : @[xx 1:1]
-          |    output x: UInt<1> @[xx 1:1]
-          |    x <= UInt(1)
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    inst a1 of A
+        |    inst a2 of A_
+        |  module A : @[yy 2:2]
+        |    output x: UInt<1> @[yy 2:2]
+        |    x <= UInt(1)
+        |  module A_ : @[xx 1:1]
+        |    output x: UInt<1> @[xx 1:1]
+        |    x <= UInt(1)
           """.stripMargin
-     execute(input, check, Seq(dontDedup("A")))
+    execute(input, check, Seq(dontDedup("A")))
   }
   "The module A and A_" should "be deduped even with different port names and info, and annotations should remapped" in {
-     val input =
-        """circuit Top :
-          |  module Top :
-          |    output out: UInt<1>
-          |    inst a1 of A
-          |    inst a2 of A_
-          |    out <= and(a1.x, a2.y)
-          |  module A : @[yy 2:2]
-          |    output x: UInt<1> @[yy 2:2]
-          |    x <= UInt(1)
-          |  module A_ : @[xx 1:1]
-          |    output y: UInt<1> @[xx 1:1]
-          |    y <= UInt(1)
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    output out: UInt<1>
+        |    inst a1 of A
+        |    inst a2 of A_
+        |    out <= and(a1.x, a2.y)
+        |  module A : @[yy 2:2]
+        |    output x: UInt<1> @[yy 2:2]
+        |    x <= UInt(1)
+        |  module A_ : @[xx 1:1]
+        |    output y: UInt<1> @[xx 1:1]
+        |    y <= UInt(1)
         """.stripMargin
-     val check =
-        """circuit Top :
-          |  module Top :
-          |    output out: UInt<1>
-          |    inst a1 of A
-          |    inst a2 of A
-          |    out <= and(a1.x, a2.x)
-          |  module A : @[yy 2:2]
-          |    output x: UInt<1> @[yy 2:2]
-          |    x <= UInt(1)
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    output out: UInt<1>
+        |    inst a1 of A
+        |    inst a2 of A
+        |    out <= and(a1.x, a2.x)
+        |  module A : @[yy 2:2]
+        |    output x: UInt<1> @[yy 2:2]
+        |    x <= UInt(1)
         """.stripMargin
 
-     val mname = ModuleName("Top", CircuitName("Top"))
-     val finalState = execute(input, check, Seq(SingleTargetDummyAnnotation(ComponentName("a2.y", mname))))
-     finalState.annotations.collect({ case d: SingleTargetDummyAnnotation => d }).head should be(SingleTargetDummyAnnotation(ComponentName("a2.x", mname)))
+    val mname = ModuleName("Top", CircuitName("Top"))
+    val finalState = execute(input, check, Seq(SingleTargetDummyAnnotation(ComponentName("a2.y", mname))))
+    finalState.annotations.collect({ case d: SingleTargetDummyAnnotation => d }).head should be(
+      SingleTargetDummyAnnotation(ComponentName("a2.x", mname))
+    )
   }
 
   "Extmodules" should "with the same defname and parameters should dedup" in {
-     val input =
-        """circuit Top :
-          |  module Top :
-          |    output out: UInt<1>
-          |    inst a1 of A
-          |    inst a2 of A_
-          |    out <= and(a1.x, a2.y)
-          |  module A : @[yy 2:2]
-          |    output x: UInt<1> @[yy 2:2]
-          |    inst b of B
-          |    x <= b.u
-          |  module A_ : @[xx 1:1]
-          |    output y: UInt<1> @[xx 1:1]
-          |    inst c of C
-          |    y <= c.u
-          |  extmodule B : @[aa 3:3]
-          |    output u : UInt<1> @[aa 4:4]
-          |    defname = BB
-          |    parameter N = 0
-          |  extmodule C : @[bb 5:5]
-          |    output u : UInt<1> @[bb 6:6]
-          |    defname = BB
-          |    parameter N = 0
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    output out: UInt<1>
+        |    inst a1 of A
+        |    inst a2 of A_
+        |    out <= and(a1.x, a2.y)
+        |  module A : @[yy 2:2]
+        |    output x: UInt<1> @[yy 2:2]
+        |    inst b of B
+        |    x <= b.u
+        |  module A_ : @[xx 1:1]
+        |    output y: UInt<1> @[xx 1:1]
+        |    inst c of C
+        |    y <= c.u
+        |  extmodule B : @[aa 3:3]
+        |    output u : UInt<1> @[aa 4:4]
+        |    defname = BB
+        |    parameter N = 0
+        |  extmodule C : @[bb 5:5]
+        |    output u : UInt<1> @[bb 6:6]
+        |    defname = BB
+        |    parameter N = 0
         """.stripMargin
-     val check =
-        """circuit Top :
-          |  module Top :
-          |    output out: UInt<1>
-          |    inst a1 of A
-          |    inst a2 of A
-          |    out <= and(a1.x, a2.x)
-          |  module A : @[yy 2:2]
-          |    output x: UInt<1> @[yy 2:2]
-          |    inst b of B
-          |    x <= b.u
-          |  extmodule B : @[aa 3:3]
-          |    output u : UInt<1> @[aa 4:4]
-          |    defname = BB
-          |    parameter N = 0
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    output out: UInt<1>
+        |    inst a1 of A
+        |    inst a2 of A
+        |    out <= and(a1.x, a2.x)
+        |  module A : @[yy 2:2]
+        |    output x: UInt<1> @[yy 2:2]
+        |    inst b of B
+        |    x <= b.u
+        |  extmodule B : @[aa 3:3]
+        |    output u : UInt<1> @[aa 4:4]
+        |    defname = BB
+        |    parameter N = 0
         """.stripMargin
 
-     execute(input, check, Seq.empty)
+    execute(input, check, Seq.empty)
   }
 
   "Extmodules" should "with the different defname or parameters should NOT dedup" in {
-     def mkfir(defnames: (String, String), params: (String, String)) =
-       s"""circuit Top :
-          |  module Top :
-          |    output out: UInt<1>
-          |    inst a1 of A
-          |    inst a2 of A_
-          |    out <= and(a1.x, a2.y)
-          |  module A : @[yy 2:2]
-          |    output x: UInt<1> @[yy 2:2]
-          |    inst b of B
-          |    x <= b.u
-          |  module A_ : @[xx 1:1]
-          |    output y: UInt<1> @[xx 1:1]
-          |    inst c of C
-          |    y <= c.u
-          |  extmodule B : @[aa 3:3]
-          |    output u : UInt<1> @[aa 4:4]
-          |    defname = ${defnames._1}
-          |    parameter N = ${params._1}
-          |  extmodule C : @[bb 5:5]
-          |    output u : UInt<1> @[bb 6:6]
-          |    defname = ${defnames._2}
-          |    parameter N = ${params._2}
+    def mkfir(defnames: (String, String), params: (String, String)) =
+      s"""circuit Top :
+         |  module Top :
+         |    output out: UInt<1>
+         |    inst a1 of A
+         |    inst a2 of A_
+         |    out <= and(a1.x, a2.y)
+         |  module A : @[yy 2:2]
+         |    output x: UInt<1> @[yy 2:2]
+         |    inst b of B
+         |    x <= b.u
+         |  module A_ : @[xx 1:1]
+         |    output y: UInt<1> @[xx 1:1]
+         |    inst c of C
+         |    y <= c.u
+         |  extmodule B : @[aa 3:3]
+         |    output u : UInt<1> @[aa 4:4]
+         |    defname = ${defnames._1}
+         |    parameter N = ${params._1}
+         |  extmodule C : @[bb 5:5]
+         |    output u : UInt<1> @[bb 6:6]
+         |    defname = ${defnames._2}
+         |    parameter N = ${params._2}
         """.stripMargin
-     val diff_defname = mkfir(("BB", "CC"), ("0", "0"))
-     execute(diff_defname, diff_defname, Seq.empty)
-     val diff_params = mkfir(("BB", "BB"), ("0", "1"))
-     execute(diff_params, diff_params, Seq.empty)
+    val diff_defname = mkfir(("BB", "CC"), ("0", "0"))
+    execute(diff_defname, diff_defname, Seq.empty)
+    val diff_params = mkfir(("BB", "BB"), ("0", "1"))
+    execute(diff_params, diff_params, Seq.empty)
   }
 
   "Modules with aggregate ports that are bulk connected" should "NOT dedup if their port names differ" in {
@@ -426,12 +428,16 @@ class DedupModuleTests extends HighTransformSpec {
         |    wire b: UInt<1>
         |    x <= b
       """.stripMargin
-    val cs = execute(input, check, Seq(
-      dontTouch(ReferenceTarget("Top", "A", Nil, "b", Nil)),
-      dontTouch(ReferenceTarget("Top", "A_", Nil, "b", Nil))
-    ))
-    cs.annotations.toSeq should contain (dontTouch(ModuleTarget("Top", "Top").instOf("a1", "A").ref("b")))
-    cs.annotations.toSeq should contain (dontTouch(ModuleTarget("Top", "Top").instOf("a2", "A").ref("b")))
+    val cs = execute(
+      input,
+      check,
+      Seq(
+        dontTouch(ReferenceTarget("Top", "A", Nil, "b", Nil)),
+        dontTouch(ReferenceTarget("Top", "A_", Nil, "b", Nil))
+      )
+    )
+    cs.annotations.toSeq should contain(dontTouch(ModuleTarget("Top", "Top").instOf("a1", "A").ref("b")))
+    cs.annotations.toSeq should contain(dontTouch(ModuleTarget("Top", "Top").instOf("a2", "A").ref("b")))
     cs.annotations.toSeq should not contain dontTouch(ReferenceTarget("Top", "A_", Nil, "b", Nil))
   }
   "The module A and A_" should "be deduped with same annotation targets when there are a lot" in {
@@ -508,12 +514,24 @@ class DedupModuleTests extends HighTransformSpec {
     val annoAB = MultiTargetDummyAnnotation(Seq(A, B), 0)
     val annoA_B_ = MultiTargetDummyAnnotation(Seq(A_, B_), 1)
     val cs = execute(input, check, Seq(annoAB, annoA_B_))
-    cs.annotations.toSeq should contain (MultiTargetDummyAnnotation(Seq(
-      Top_a1, Top_a1_b
-    ), 0))
-    cs.annotations.toSeq should contain (MultiTargetDummyAnnotation(Seq(
-      Top_a2, Top_a2_b
-    ), 1))
+    cs.annotations.toSeq should contain(
+      MultiTargetDummyAnnotation(
+        Seq(
+          Top_a1,
+          Top_a1_b
+        ),
+        0
+      )
+    )
+    cs.annotations.toSeq should contain(
+      MultiTargetDummyAnnotation(
+        Seq(
+          Top_a2,
+          Top_a2_b
+        ),
+        1
+      )
+    )
   }
   "The module A and A_" should "be deduped with same annotations with same multi-targets, that share roots" in {
     val input =
@@ -555,15 +573,25 @@ class DedupModuleTests extends HighTransformSpec {
     val annoA = MultiTargetDummyAnnotation(Seq(A, A.instOf("b", "B")), 0)
     val annoA_ = MultiTargetDummyAnnotation(Seq(A_, A_.instOf("b", "B_")), 1)
     val cs = execute(input, check, Seq(annoA, annoA_))
-    cs.annotations.toSeq should contain (MultiTargetDummyAnnotation(Seq(
-      Top.module("Top").instOf("a1", "A"),
-      Top.module("Top").instOf("a1", "A").instOf("b", "B")
-    ),0))
-    cs.annotations.toSeq should contain (MultiTargetDummyAnnotation(Seq(
-      Top.module("Top").instOf("a2", "A"),
-      Top.module("Top").instOf("a2", "A").instOf("b", "B")
-    ),1))
-    cs.deletedAnnotations.isEmpty should be (true)
+    cs.annotations.toSeq should contain(
+      MultiTargetDummyAnnotation(
+        Seq(
+          Top.module("Top").instOf("a1", "A"),
+          Top.module("Top").instOf("a1", "A").instOf("b", "B")
+        ),
+        0
+      )
+    )
+    cs.annotations.toSeq should contain(
+      MultiTargetDummyAnnotation(
+        Seq(
+          Top.module("Top").instOf("a2", "A"),
+          Top.module("Top").instOf("a2", "A").instOf("b", "B")
+        ),
+        1
+      )
+    )
+    cs.deletedAnnotations.isEmpty should be(true)
   }
   "The deduping module A and A_" should "rename internal signals that have different names" in {
     val input =
@@ -600,12 +628,12 @@ class DedupModuleTests extends HighTransformSpec {
     val Top = CircuitTarget("Top")
     val A = Top.module("A")
     val A_ = Top.module("A_")
-    val annoA  = SingleTargetDummyAnnotation(A.ref("a"))
+    val annoA = SingleTargetDummyAnnotation(A.ref("a"))
     val annoA_ = SingleTargetDummyAnnotation(A_.ref("b"))
     val cs = execute(input, check, Seq(annoA, annoA_))
-    cs.annotations.toSeq should contain (annoA)
+    cs.annotations.toSeq should contain(annoA)
     cs.annotations.toSeq should not contain (SingleTargetDummyAnnotation(A.ref("b")))
-    cs.deletedAnnotations.isEmpty should be (true)
+    cs.deletedAnnotations.isEmpty should be(true)
   }
   "main" should "not be deduped even if it's the last module" in {
     val input =
@@ -691,14 +719,25 @@ class DedupModuleTests extends HighTransformSpec {
     val anno1 = MultiTargetDummyAnnotation(Seq(inst1, ref1), 0)
     val anno2 = MultiTargetDummyAnnotation(Seq(inst2, ref2), 1)
     val cs = execute(input, check, Seq(anno1, anno2))
-    cs.annotations.toSeq should contain (MultiTargetDummyAnnotation(Seq(
-      inst1, ref1
-    ),0))
-    cs.annotations.toSeq should contain (MultiTargetDummyAnnotation(Seq(
-      Top.module("Top").instOf("a_", "A").instOf("b", "B"),
-      Top.module("Top").instOf("a_", "A").instOf("b", "B").ref("foo")
-    ),1))
-    cs.deletedAnnotations.isEmpty should be (true)
+    cs.annotations.toSeq should contain(
+      MultiTargetDummyAnnotation(
+        Seq(
+          inst1,
+          ref1
+        ),
+        0
+      )
+    )
+    cs.annotations.toSeq should contain(
+      MultiTargetDummyAnnotation(
+        Seq(
+          Top.module("Top").instOf("a_", "A").instOf("b", "B"),
+          Top.module("Top").instOf("a_", "A").instOf("b", "B").ref("foo")
+        ),
+        1
+      )
+    )
+    cs.deletedAnnotations.isEmpty should be(true)
   }
 
   "The deduping module A and A_" should "rename nested instances that have different names" in {
@@ -746,14 +785,25 @@ class DedupModuleTests extends HighTransformSpec {
     val anno1 = MultiTargetDummyAnnotation(Seq(inst1, ref1), 0)
     val anno2 = MultiTargetDummyAnnotation(Seq(inst2, ref2), 1)
     val cs = execute(input, check, Seq(anno1, anno2))
-    cs.annotations.toSeq should contain (MultiTargetDummyAnnotation(Seq(
-      inst1, ref1
-    ),0))
-    cs.annotations.toSeq should contain (MultiTargetDummyAnnotation(Seq(
-      Top.module("Top").instOf("a_", "A").instOf("b", "B").instOf("c", "C").instOf("d", "D"),
-      Top.module("Top").instOf("a_", "A").instOf("b", "B").instOf("c", "C").instOf("d", "D").ref("foo")
-    ),1))
-    cs.deletedAnnotations.isEmpty should be (true)
+    cs.annotations.toSeq should contain(
+      MultiTargetDummyAnnotation(
+        Seq(
+          inst1,
+          ref1
+        ),
+        0
+      )
+    )
+    cs.annotations.toSeq should contain(
+      MultiTargetDummyAnnotation(
+        Seq(
+          Top.module("Top").instOf("a_", "A").instOf("b", "B").instOf("c", "C").instOf("d", "D"),
+          Top.module("Top").instOf("a_", "A").instOf("b", "B").instOf("c", "C").instOf("d", "D").ref("foo")
+        ),
+        1
+      )
+    )
+    cs.deletedAnnotations.isEmpty should be(true)
   }
 
   "Deduping modules with multiple instances" should "corectly rename instances" in {
@@ -801,50 +851,55 @@ class DedupModuleTests extends HighTransformSpec {
     val cInstances = bInstances.map(_.instOf("c", "C"))
     val annos = MultiTargetDummyAnnotation(bInstances ++ cInstances, 0)
     val cs = execute(input, check, Seq(annos))
-    cs.annotations.toSeq should contain (MultiTargetDummyAnnotation(Seq(
-      Top.instOf("b", "B"),
-      Top.instOf("b_", "B"),
-      Top.instOf("a1", "A").instOf("b_", "B"),
-      Top.instOf("a2", "A").instOf("b_", "B"),
-      Top.instOf("a1", "A").instOf("b", "B"),
-      Top.instOf("a2", "A").instOf("b", "B"),
-      Top.instOf("b", "B").instOf("c", "C"),
-      Top.instOf("b_", "B").instOf("c", "C"),
-      Top.instOf("a1", "A").instOf("b_", "B").instOf("c", "C"),
-      Top.instOf("a2", "A").instOf("b_", "B").instOf("c", "C"),
-      Top.instOf("a1", "A").instOf("b", "B").instOf("c", "C"),
-      Top.instOf("a2", "A").instOf("b", "B").instOf("c", "C")
-    ),0))
-    cs.deletedAnnotations.isEmpty should be (true)
+    cs.annotations.toSeq should contain(
+      MultiTargetDummyAnnotation(
+        Seq(
+          Top.instOf("b", "B"),
+          Top.instOf("b_", "B"),
+          Top.instOf("a1", "A").instOf("b_", "B"),
+          Top.instOf("a2", "A").instOf("b_", "B"),
+          Top.instOf("a1", "A").instOf("b", "B"),
+          Top.instOf("a2", "A").instOf("b", "B"),
+          Top.instOf("b", "B").instOf("c", "C"),
+          Top.instOf("b_", "B").instOf("c", "C"),
+          Top.instOf("a1", "A").instOf("b_", "B").instOf("c", "C"),
+          Top.instOf("a2", "A").instOf("b_", "B").instOf("c", "C"),
+          Top.instOf("a1", "A").instOf("b", "B").instOf("c", "C"),
+          Top.instOf("a2", "A").instOf("b", "B").instOf("c", "C")
+        ),
+        0
+      )
+    )
+    cs.deletedAnnotations.isEmpty should be(true)
   }
 
   "dedup" should "properly rename target components after retyping" in {
     val input = """
-      |circuit top:
-      |  module top:
-      |    input ia: {z: {y: {x: UInt<1>}}, a: UInt<1>}
-      |    input ib: {a: {b: {c: UInt<1>}}, z: UInt<1>}
-      |    output oa: {z: {y: {x: UInt<1>}}, a: UInt<1>}
-      |    output ob: {a: {b: {c: UInt<1>}}, z: UInt<1>}
-      |    inst a of a
-      |    a.i.z.y.x <= ia.z.y.x
-      |    a.i.a <= ia.a
-      |    oa.z.y.x <= a.o.z.y.x
-      |    oa.a <= a.o.a
-      |    inst b of b
-      |    b.q.a.b.c <= ib.a.b.c
-      |    b.q.z <= ib.z
-      |    ob.a.b.c <= b.r.a.b.c
-      |    ob.z <= b.r.z
-      |  module a:
-      |    input i: {z: {y: {x: UInt<1>}}, a: UInt<1>}
-      |    output o: {z: {y: {x: UInt<1>}}, a: UInt<1>}
-      |    o <= i
-      |  module b:
-      |    input q: {a: {b: {c: UInt<1>}}, z: UInt<1>}
-      |    output r: {a: {b: {c: UInt<1>}}, z: UInt<1>}
-      |    r <= q
-      |""".stripMargin
+                  |circuit top:
+                  |  module top:
+                  |    input ia: {z: {y: {x: UInt<1>}}, a: UInt<1>}
+                  |    input ib: {a: {b: {c: UInt<1>}}, z: UInt<1>}
+                  |    output oa: {z: {y: {x: UInt<1>}}, a: UInt<1>}
+                  |    output ob: {a: {b: {c: UInt<1>}}, z: UInt<1>}
+                  |    inst a of a
+                  |    a.i.z.y.x <= ia.z.y.x
+                  |    a.i.a <= ia.a
+                  |    oa.z.y.x <= a.o.z.y.x
+                  |    oa.a <= a.o.a
+                  |    inst b of b
+                  |    b.q.a.b.c <= ib.a.b.c
+                  |    b.q.z <= ib.z
+                  |    ob.a.b.c <= b.r.a.b.c
+                  |    ob.z <= b.r.z
+                  |  module a:
+                  |    input i: {z: {y: {x: UInt<1>}}, a: UInt<1>}
+                  |    output o: {z: {y: {x: UInt<1>}}, a: UInt<1>}
+                  |    o <= i
+                  |  module b:
+                  |    input q: {a: {b: {c: UInt<1>}}, z: UInt<1>}
+                  |    output r: {a: {b: {c: UInt<1>}}, z: UInt<1>}
+                  |    r <= q
+                  |""".stripMargin
 
     case class DummyRTAnnotation(target: ReferenceTarget) extends SingleTargetAnnotation[ReferenceTarget] {
       def duplicate(n: ReferenceTarget) = DummyRTAnnotation(n)
@@ -853,7 +908,6 @@ class DedupModuleTests extends HighTransformSpec {
     val annA = DummyRTAnnotation(ReferenceTarget("top", "a", Nil, "i", Seq(TargetToken.Field("a"))))
     val annB = DummyRTAnnotation(ReferenceTarget("top", "b", Nil, "q", Seq(TargetToken.Field("a"))))
 
-
     val cs = CircuitState(Parser.parseString(input, Parser.IgnoreInfo), Seq(annA, annB))
 
     val deduper = new stage.transforms.Compiler(stage.Forms.Deduped, Nil)
@@ -871,7 +925,7 @@ class DedupModuleTests extends HighTransformSpec {
     val bPath = Seq((TargetToken.Instance("b"), TargetToken.OfModule("a")))
     val expectedAnnA = DummyRTAnnotation(ReferenceTarget("top", "top", aPath, "i", Seq(TargetToken.Field("a"))))
     val expectedAnnB = DummyRTAnnotation(ReferenceTarget("top", "top", aPath, "i", Seq(TargetToken.Field("a"))))
-    csDeduped.annotations.toSeq should contain (expectedAnnA)
-    csDeduped.annotations.toSeq should contain (expectedAnnB)
+    csDeduped.annotations.toSeq should contain(expectedAnnA)
+    csDeduped.annotations.toSeq should contain(expectedAnnB)
   }
 }