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authorSchuyler Eldridge2019-08-01 21:25:11 -0400
committerGitHub2019-08-01 21:25:11 -0400
commitac42287bc47fb8bc6695ae0aaf8f4fee61e129e5 (patch)
tree9c14023a5b242c391ece9063d3bcae7e012deab7 /src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
parent86d2470d8294a4dba37d33ba021558ba33da4d65 (diff)
parent2bf399c240938ba51069348f986fa5d65135a808 (diff)
Merge pull request #1143 from freechipsproject/replace-io-source-with-fileutils
Followup to PR #1142
Diffstat (limited to 'src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala')
-rw-r--r--src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala b/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
index 089e837a..6e63317b 100644
--- a/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
@@ -6,6 +6,7 @@ import firrtl.annotations.{Annotation, CircuitName, ModuleName}
import firrtl.transforms._
import firrtl.{FIRRTLException, Transform, VerilogCompiler, VerilogEmitter}
import firrtlTests.{HighTransformSpec, LowTransformSpec}
+import firrtl.FileUtils
import org.scalacheck.Test.Failed
import org.scalatest.{FreeSpec, Matchers, Succeeded}
@@ -132,9 +133,7 @@ class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec {
// but our file list should not include the verilog header file.
val fileListFile = new java.io.File(s"test_run_dir/${BlackBoxSourceHelper.defaultFileListName}")
fileListFile.exists should be (true)
- val fileListFileSource = io.Source.fromFile(fileListFile)
- val fileList = fileListFileSource.getLines.mkString
- fileListFileSource.close()
+ val fileList = FileUtils.getText(fileListFile)
fileList.contains("ParameterizedViaHeaderAdderExtModule.v") should be (true)
fileList.contains("VerilogHeaderFile.vh") should be (false)
}