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| author | Jack Koenig | 2020-08-15 10:16:28 -0700 |
|---|---|---|
| committer | GitHub | 2020-08-15 10:16:28 -0700 |
| commit | f1c314e6c7e116df33ffc215ec907212037292dc (patch) | |
| tree | f06060e9fb52f4f5b30bc56db78acb6bd371642d /src/test/scala/firrtlTests/execution/VerilogExecution.scala | |
| parent | 2e5f942d25d7afab79ee1263c5d6833cad9d743d (diff) | |
| parent | 9adbe1ede59f9aeb25e71fd8318a4e7e46c4cc34 (diff) | |
Merge pull request #1852 from freechipsproject/format-src-4
Apply Scalafmt Rewriting
Diffstat (limited to 'src/test/scala/firrtlTests/execution/VerilogExecution.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/execution/VerilogExecution.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/execution/VerilogExecution.scala b/src/test/scala/firrtlTests/execution/VerilogExecution.scala index 89f27609..913cfc71 100644 --- a/src/test/scala/firrtlTests/execution/VerilogExecution.scala +++ b/src/test/scala/firrtlTests/execution/VerilogExecution.scala @@ -30,7 +30,7 @@ trait VerilogExecution extends TestExecution { // Make and run Verilog simulation verilogToCpp(c.main, testDir, Nil, harness) #&& - cppToExe(c.main, testDir) ! loggingProcessLogger + cppToExe(c.main, testDir) ! loggingProcessLogger assert(executeExpectingSuccess(c.main, testDir)) } } |