Merge pull request #932 from seldridge/f269

- Add Target.prettyPrint method
- Improve UninferredWidth exception message

1 files changed, 27 insertions, 1 deletions

diff --git a/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala b/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala
index 4ae4e036..da154b6a 100644
--- a/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala
+++ b/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala
@@ -55,5 +55,31 @@ class TargetSpec extends FirrtlPropSpec {
       assert(Target.deserialize(t.serialize) == t, s"$t does not properly serialize/deserialize")
     }
   }
+  property("Pretty Printer should work") {
+    val circuit = CircuitTarget("A")
+    val top = circuit.module("B")
+    val targets = Seq(
+      (circuit, "circuit A:"),
+      (top,
+       """|circuit A:
+          |└── module B:""".stripMargin),
+      (top.instOf("c", "C"),
+       """|circuit A:
+          |└── module B:
+          |    └── inst c of C:""".stripMargin),
+      (top.ref("r"),
+       """|circuit A:
+          |└── module B:
+          |    └── r""".stripMargin),
+      (top.ref("r").index(1).field("hi").clock,
+       """|circuit A:
+          |└── module B:
+          |    └── r[1].hi@clock""".stripMargin),
+      (GenericTarget(None, None, Vector(Ref("r"))),
+       """|circuit ???:
+          |└── module ???:
+          |    └── r""".stripMargin)
+    )
+    targets.foreach { case (t, str) => assert(t.prettyPrint() == str, s"$t didn't properly prettyPrint") }
+  }
 }
-