diff options
| author | Schuyler Eldridge | 2019-07-17 14:08:33 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2019-09-16 17:12:51 -0400 |
| commit | a594ccef986c4567730fee729bdea9ed9aefed38 (patch) | |
| tree | 2512913e054ea7d56867f2c73912ff4be17f1e82 /src/test/scala/firrtlTests/ZeroWidthTests.scala | |
| parent | 7e39ea8ec948ff1db7ccd0d850923a86d2d8a4e7 (diff) | |
Rename gender to flow
The following names are changed:
- gender -> flow
- Gender -> Flow
- MALE -> SourceFlow
- FEMALE -> SinkFlow
- BIGENDER -> DuplexFlow
- UNKNOWNGENDER -> UnknownFlow
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/test/scala/firrtlTests/ZeroWidthTests.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/ZeroWidthTests.scala | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/test/scala/firrtlTests/ZeroWidthTests.scala b/src/test/scala/firrtlTests/ZeroWidthTests.scala index eb955f29..eb3d1a96 100644 --- a/src/test/scala/firrtlTests/ZeroWidthTests.scala +++ b/src/test/scala/firrtlTests/ZeroWidthTests.scala @@ -15,7 +15,7 @@ class ZeroWidthTests extends FirrtlFlatSpec { ToWorkingIR, ResolveKinds, InferTypes, - ResolveGenders, + ResolveFlows, new InferWidths, ZeroWidth) private def exec (input: String) = { @@ -218,12 +218,12 @@ class ZeroWidthVerilog extends FirrtlFlatSpec { "Circuit" should "accept zero width wires" in { val compiler = new VerilogCompiler val input = - """circuit Top : - | module Top : + """circuit Top : + | module Top : | input y: UInt<0> | output x: UInt<3> | x <= y""".stripMargin - val check = + val check = """module Top( | output [2:0] x |); |