All of src/ formatted with scalafmt

1 files changed, 35 insertions, 38 deletions

diff --git a/src/test/scala/firrtlTests/ZeroWidthTests.scala b/src/test/scala/firrtlTests/ZeroWidthTests.scala
index b53f55ea..3c3df5ca 100644
--- a/src/test/scala/firrtlTests/ZeroWidthTests.scala
+++ b/src/test/scala/firrtlTests/ZeroWidthTests.scala
@@ -7,20 +7,17 @@ import firrtl.passes._
 import firrtl.testutils._
 
 class ZeroWidthTests extends FirrtlFlatSpec {
-  def transforms = Seq(
-      ToWorkingIR,
-      ResolveKinds,
-      InferTypes,
-      ResolveFlows,
-      new InferWidths,
-      ZeroWidth)
-  private def exec (input: String) = {
+  def transforms = Seq(ToWorkingIR, ResolveKinds, InferTypes, ResolveFlows, new InferWidths, ZeroWidth)
+  private def exec(input: String) = {
     val circuit = parse(input)
-    transforms.foldLeft(CircuitState(circuit, UnknownForm)) {
-      (c: CircuitState, p: Transform) => p.runTransform(c)
-    }.circuit.serialize
-  }
-   // =============================
+    transforms
+      .foldLeft(CircuitState(circuit, UnknownForm)) { (c: CircuitState, p: Transform) =>
+        p.runTransform(c)
+      }
+      .circuit
+      .serialize
+  }
+  // =============================
   "Zero width port" should " be deleted" in {
     val input =
       """circuit Top :
@@ -30,10 +27,10 @@ class ZeroWidthTests extends FirrtlFlatSpec {
         |    x <= y""".stripMargin
     val check =
       """circuit Top :
-         |  module Top :
-         |    output x : UInt<1>
-         |    x <= UInt<1>(0)""".stripMargin
-      (parse(exec(input))) should be (parse(check))
+        |  module Top :
+        |    output x : UInt<1>
+        |    x <= UInt<1>(0)""".stripMargin
+    (parse(exec(input))) should be(parse(check))
   }
   "Add of <0> and <2> " should " put in zero" in {
     val input =
@@ -47,7 +44,7 @@ class ZeroWidthTests extends FirrtlFlatSpec {
         |  module Top :
         |    output x : UInt<3>
         |    x <= add(UInt<1>(0), UInt<2>(2))""".stripMargin
-      (parse(exec(input)).serialize) should be (parse(check).serialize)
+    (parse(exec(input)).serialize) should be(parse(check).serialize)
   }
   "Mux on <0>" should "put in zero" in {
     val input =
@@ -61,7 +58,7 @@ class ZeroWidthTests extends FirrtlFlatSpec {
         |  module Top :
         |    output x : UInt<2>
         |    x <= mux(UInt<1>(0), UInt<2>(2), UInt<2>(1))""".stripMargin
-      (parse(exec(input)).serialize) should be (parse(check).serialize)
+    (parse(exec(input)).serialize) should be(parse(check).serialize)
   }
   "Bundle with field of <0>" should "get deleted" in {
     val input =
@@ -75,7 +72,7 @@ class ZeroWidthTests extends FirrtlFlatSpec {
         |  module Top :
         |    output x : { b: UInt<1> }
         |    skip""".stripMargin
-      (parse(exec(input)).serialize) should be (parse(check).serialize)
+    (parse(exec(input)).serialize) should be(parse(check).serialize)
   }
   "Vector with type of <0>" should "get deleted" in {
     val input =
@@ -88,7 +85,7 @@ class ZeroWidthTests extends FirrtlFlatSpec {
       """circuit Top :
         |  module Top :
         |    skip""".stripMargin
-      (parse(exec(input)).serialize) should be (parse(check).serialize)
+    (parse(exec(input)).serialize) should be(parse(check).serialize)
   }
   "Node with <0>" should "be removed" in {
     val input =
@@ -100,7 +97,7 @@ class ZeroWidthTests extends FirrtlFlatSpec {
       """circuit Top :
         |  module Top :
         |    skip""".stripMargin
-      (parse(exec(input)).serialize) should be (parse(check).serialize)
+    (parse(exec(input)).serialize) should be(parse(check).serialize)
   }
   "IsInvalid on <0>" should "be deleted" in {
     val input =
@@ -112,7 +109,7 @@ class ZeroWidthTests extends FirrtlFlatSpec {
       """circuit Top :
         |  module Top :
         |    skip""".stripMargin
-      (parse(exec(input)).serialize) should be (parse(check).serialize)
+    (parse(exec(input)).serialize) should be(parse(check).serialize)
   }
   "Expression in node with type <0>" should "be replaced by UInt<1>(0)" in {
     val input =
@@ -126,7 +123,7 @@ class ZeroWidthTests extends FirrtlFlatSpec {
         |  module Top :
         |    input x: UInt<1>
         |    node z = add(x, UInt<1>(0))""".stripMargin
-      (parse(exec(input)).serialize) should be (parse(check).serialize)
+    (parse(exec(input)).serialize) should be(parse(check).serialize)
   }
   "Expression in cat with type <0>" should "be removed" in {
     val input =
@@ -140,7 +137,7 @@ class ZeroWidthTests extends FirrtlFlatSpec {
         |  module Top :
         |    input x: UInt<1>
         |    node z = x""".stripMargin
-      (parse(exec(input)).serialize) should be (parse(check).serialize)
+    (parse(exec(input)).serialize) should be(parse(check).serialize)
   }
   "Nested cats with type <0>" should "be removed" in {
     val input =
@@ -154,7 +151,7 @@ class ZeroWidthTests extends FirrtlFlatSpec {
       """circuit Top :
         |  module Top :
         |    skip""".stripMargin
-      (parse(exec(input)).serialize) should be (parse(check).serialize)
+    (parse(exec(input)).serialize) should be(parse(check).serialize)
   }
   "Nested cats where one has type <0>" should "be unaffected" in {
     val input =
@@ -170,7 +167,7 @@ class ZeroWidthTests extends FirrtlFlatSpec {
         |    input x: UInt<1>
         |    input z: UInt<1>
         |    node a = cat(x, z)""".stripMargin
-      (parse(exec(input)).serialize) should be (parse(check).serialize)
+    (parse(exec(input)).serialize) should be(parse(check).serialize)
   }
   "Stop with type <0>" should "be replaced with UInt(0)" in {
     val input =
@@ -188,7 +185,7 @@ class ZeroWidthTests extends FirrtlFlatSpec {
         |    input x: UInt<1>
         |    input z: UInt<1>
         |    stop(clk, UInt(0), 1)""".stripMargin
-      (parse(exec(input)).serialize) should be (parse(check).serialize)
+    (parse(exec(input)).serialize) should be(parse(check).serialize)
   }
   "Print with type <0>" should "be replaced with UInt(0)" in {
     val input =
@@ -206,7 +203,7 @@ class ZeroWidthTests extends FirrtlFlatSpec {
         |    input x: UInt<1>
         |    input z: UInt<1>
         |    printf(clk, UInt(1), "%d %d %d\n", x, UInt(0), z)""".stripMargin
-      (parse(exec(input)).serialize) should be (parse(check).serialize)
+    (parse(exec(input)).serialize) should be(parse(check).serialize)
   }
 
   "Andr of zero-width expression" should "return true" in {
@@ -218,10 +215,10 @@ class ZeroWidthTests extends FirrtlFlatSpec {
         |    x <= andr(y)""".stripMargin
     val check =
       """circuit Top :
-         |  module Top :
-         |    output x : UInt<1>
-         |    x <= UInt<1>(1)""".stripMargin
-      (parse(exec(input))) should be (parse(check))
+        |  module Top :
+        |    output x : UInt<1>
+        |    x <= UInt<1>(1)""".stripMargin
+    (parse(exec(input))) should be(parse(check))
   }
 }
 
@@ -230,17 +227,17 @@ class ZeroWidthVerilog extends FirrtlFlatSpec {
     val compiler = new VerilogCompiler
     val input =
       """circuit Top :
-         |  module Top :
-         |    input y: UInt<0>
-         |    output x: UInt<3>
-         |    x <= y""".stripMargin
+        |  module Top :
+        |    input y: UInt<0>
+        |    output x: UInt<3>
+        |    x <= y""".stripMargin
     val check =
       """module Top(
         |  output  [2:0] x
         |);
         |  assign x = 3'h0;
         |endmodule
-        |""".stripMargin.split("\n") map normalized
+        |""".stripMargin.split("\n").map(normalized)
     executeTest(input, check, compiler)
   }
 }