diff options
| author | Jack Koenig | 2018-02-27 18:07:11 -0800 |
|---|---|---|
| committer | GitHub | 2018-02-27 18:07:11 -0800 |
| commit | c7eb1570dfb1c7701ea32d1209982a053f3cec1d (patch) | |
| tree | 3f509b202d82841c5dad5588d1f953a25d389b44 /src/test/scala/firrtlTests/WiringTests.scala | |
| parent | b90fc784a1819c1d7905910130a7da022214bc22 (diff) | |
Refactor Annotations (#721)
- Old Annotation renamed to deprecated LegacyAnnotation
- Annotation is now a trait that can be extended
- New JsonProtocol for Annotation [de]serialization
- Replace AnnotationMap with AnnotationSeq
- Deprecate Transform.getMyAnnotations
- Update Transforms
- Turn on deprecation warnings
- Remove deprecated Driver.compile
- Make AnnotationTests abstract with Legacy and Json subclasses
- Add functionality to convert LegacyAnnotations of built-in annos
This will give a noisy warning and is more of a best effort than a
robust solution.
Fixes #475 Closes #609
Diffstat (limited to 'src/test/scala/firrtlTests/WiringTests.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/WiringTests.scala | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/test/scala/firrtlTests/WiringTests.scala b/src/test/scala/firrtlTests/WiringTests.scala index 6da73157..4f8fd9fe 100644 --- a/src/test/scala/firrtlTests/WiringTests.scala +++ b/src/test/scala/firrtlTests/WiringTests.scala @@ -705,7 +705,7 @@ class WiringTests extends FirrtlFlatSpec { (c: Circuit, p: Pass) => p.run(c) } val wiringXForm = new WiringTransform() - val retC = wiringXForm.execute(CircuitState(c, MidForm, Some(AnnotationMap(Seq(source, sink))), None)).circuit + val retC = wiringXForm.execute(CircuitState(c, MidForm, Seq(source, sink))).circuit (parse(retC.serialize).serialize) should be (parse(check).serialize) } @@ -743,7 +743,7 @@ class WiringTests extends FirrtlFlatSpec { (c: Circuit, p: Pass) => p.run(c) } val wiringXForm = new WiringTransform() - val retC = wiringXForm.execute(CircuitState(c, MidForm, Some(AnnotationMap(Seq(source, sink))), None)).circuit + val retC = wiringXForm.execute(CircuitState(c, MidForm, Seq(source, sink))).circuit (parse(retC.serialize).serialize) should be (parse(check).serialize) } @@ -789,7 +789,7 @@ class WiringTests extends FirrtlFlatSpec { (c: Circuit, p: Pass) => p.run(c) } val wiringXForm = new WiringTransform() - val retC = wiringXForm.execute(CircuitState(c, MidForm, Some(AnnotationMap(Seq(source, sink))), None)).circuit + val retC = wiringXForm.execute(CircuitState(c, MidForm, Seq(source, sink))).circuit (parse(retC.serialize).serialize) should be (parse(check).serialize) } |
