Add Width Constraints with Annotations (#956)

* refactor InferWidths to allow for extra contraints, add InferWidthsWithAnnos

* add test cases

* add ResolvedAnnotationPaths trait to InferWidthsWithAnnos

* remove println

* cleanup tests

* remove extraneous constraints

* use foreachStmt instead of mapStmt

* remove support for aggregates

* fold InferWidthsWithAnnos into InferWidths

* throw exception if ref not found, check for annos before AST walk

1 files changed, 45 insertions, 88 deletions

diff --git a/src/test/scala/firrtlTests/WiringTests.scala b/src/test/scala/firrtlTests/WiringTests.scala
index 4f8fd9fe..4fe4a46c 100644
--- a/src/test/scala/firrtlTests/WiringTests.scala
+++ b/src/test/scala/firrtlTests/WiringTests.scala
@@ -14,15 +14,19 @@ import wiring.WiringUtils._
 import wiring._
 
 class WiringTests extends FirrtlFlatSpec {
-  private def executeTest(input: String, expected: Seq[String], passes: Seq[Pass]) = {
-    val c = passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
-      (c: Circuit, p: Pass) => p.run(c)
-    }
-    val lines = c.serialize.split("\n") map normalized
+  private def executeTest(input: String,
+    expected: String,
+    passes: Seq[Transform],
+    annos: Seq[Annotation]): Unit = {
+    val c = passes.foldLeft(CircuitState(Parser.parse(input.split("\n").toIterator), UnknownForm, annos)) {
+      (c: CircuitState, p: Transform) => p.runTransform(c)
+    }.circuit
 
-    expected foreach { e =>
-      lines should contain(e)
-    }
+    (parse(c.serialize).serialize) should be (parse(expected).serialize)
+  }
+
+  private def executeTest(input: String, expected: String, passes: Seq[Transform]): Unit = {
+    executeTest(input, expected, passes, Seq.empty)
   }
 
   def passes = Seq(
@@ -30,7 +34,7 @@ class WiringTests extends FirrtlFlatSpec {
     ResolveKinds,
     InferTypes,
     ResolveGenders,
-    InferWidths
+    new InferWidths
   )
 
   it should "wire from a register source (r) to multiple extmodule sinks (X)" in {
@@ -114,12 +118,9 @@ class WiringTests extends FirrtlFlatSpec {
          |    input clock: Clock
          |    input pin: UInt<5>
          |""".stripMargin
-    val c = passes.foldLeft(parse(input)) {
-      (c: Circuit, p: Pass) => p.run(c)
-    }
+
     val wiringPass = new Wiring(Seq(sas))
-    val retC = wiringPass.run(c)
-    (parse(retC.serialize).serialize) should be (parse(check).serialize)
+    executeTest(input, check, passes :+ wiringPass)
   }
 
   it should "wire from a register source (r) to multiple module sinks (X)" in {
@@ -203,12 +204,9 @@ class WiringTests extends FirrtlFlatSpec {
          |    input clock: Clock
          |    input pin: UInt<5>
          |""".stripMargin
-    val c = passes.foldLeft(parse(input)) {
-      (c: Circuit, p: Pass) => p.run(c)
-    }
+
     val wiringPass = new Wiring(Seq(sas))
-    val retC = wiringPass.run(c)
-    (parse(retC.serialize).serialize) should be (parse(check).serialize)
+    executeTest(input, check, passes :+ wiringPass)
   }
 
   it should "wire from a register sink (r) to a wire source (s) in another module (X)" in {
@@ -295,12 +293,9 @@ class WiringTests extends FirrtlFlatSpec {
          |    wire s: UInt<5>
          |    s <= pin
          |""".stripMargin
-    val c = passes.foldLeft(parse(input)) {
-      (c: Circuit, p: Pass) => p.run(c)
-    }
+
     val wiringPass = new Wiring(Seq(sas))
-    val retC = wiringPass.run(c)
-    (parse(retC.serialize).serialize) should be (parse(check).serialize)
+    executeTest(input, check, passes :+ wiringPass)
   }
 
   it should "wire from a SubField source (r.x) to an extmodule sink (X)" in {
@@ -339,12 +334,9 @@ class WiringTests extends FirrtlFlatSpec {
          |    input clock: Clock
          |    input pin: UInt<5>
          |""".stripMargin
-    val c = passes.foldLeft(parse(input)) {
-      (c: Circuit, p: Pass) => p.run(c)
-    }
+
     val wiringPass = new Wiring(Seq(sas))
-    val retC = wiringPass.run(c)
-    (parse(retC.serialize).serialize) should be (parse(check).serialize)
+    executeTest(input, check, passes :+ wiringPass)
   }
 
   it should "wire properly with a source as a submodule of a sink" in {
@@ -386,12 +378,9 @@ class WiringTests extends FirrtlFlatSpec {
          |    reg r: UInt<5>, clock
          |    r_0 <= r
          |""".stripMargin
-    val c = passes.foldLeft(parse(input)) {
-      (c: Circuit, p: Pass) => p.run(c)
-    }
+
     val wiringPass = new Wiring(Seq(sas))
-    val retC = wiringPass.run(c)
-    (parse(retC.serialize).serialize) should be (parse(check).serialize)
+    executeTest(input, check, passes :+ wiringPass)
   }
 
   it should "wire with source and sink in the same module" in {
@@ -415,12 +404,9 @@ class WiringTests extends FirrtlFlatSpec {
          |    s <= pin
          |    pin <= r
          |""".stripMargin
-    val c = passes.foldLeft(parse(input)) {
-      (c: Circuit, p: Pass) => p.run(c)
-    }
+
     val wiringPass = new Wiring(Seq(sas))
-    val retC = wiringPass.run(c)
-    (parse(retC.serialize).serialize) should be (parse(check).serialize)
+    executeTest(input, check, passes :+ wiringPass)
   }
 
   it should "wire multiple sinks in the same module" in {
@@ -456,12 +442,9 @@ class WiringTests extends FirrtlFlatSpec {
          |    s <= pin
          |    pin <= r
          |""".stripMargin
-    val c = passes.foldLeft(parse(input)) {
-      (c: Circuit, p: Pass) => p.run(c)
-    }
+
     val wiringPass = new Wiring(Seq(sas))
-    val retC = wiringPass.run(c)
-    (parse(retC.serialize).serialize) should be (parse(check).serialize)
+    executeTest(input, check, passes :+ wiringPass)
   }
 
   it should "wire clocks" in {
@@ -498,12 +481,9 @@ class WiringTests extends FirrtlFlatSpec {
          |    input clock: Clock
          |    input pin: Clock
          |""".stripMargin
-    val c = passes.foldLeft(parse(input)) {
-      (c: Circuit, p: Pass) => p.run(c)
-    }
+
     val wiringPass = new Wiring(Seq(sas))
-    val retC = wiringPass.run(c)
-    (parse(retC.serialize).serialize) should be (parse(check).serialize)
+    executeTest(input, check, passes :+ wiringPass)
   }
 
   it should "handle two source instances with clearly defined sinks" in {
@@ -544,12 +524,9 @@ class WiringTests extends FirrtlFlatSpec {
          |    input clock: Clock
          |    input pin: Clock
          |""".stripMargin
-    val c = passes.foldLeft(parse(input)) {
-      (c: Circuit, p: Pass) => p.run(c)
-    }
+
     val wiringPass = new Wiring(Seq(sas))
-    val retC = wiringPass.run(c)
-    (parse(retC.serialize).serialize) should be (parse(check).serialize)
+    executeTest(input, check, passes :+ wiringPass)
   }
 
   it should "wire multiple clocks" in {
@@ -590,12 +567,9 @@ class WiringTests extends FirrtlFlatSpec {
          |    input clock: Clock
          |    input pin: Clock
          |""".stripMargin
-    val c = passes.foldLeft(parse(input)) {
-      (c: Circuit, p: Pass) => p.run(c)
-    }
+
     val wiringPass = new Wiring(Seq(sas))
-    val retC = wiringPass.run(c)
-    (parse(retC.serialize).serialize) should be (parse(check).serialize)
+    executeTest(input, check, passes :+ wiringPass)
   }
 
   it should "error with WiringException for indeterminate ownership" in {
@@ -619,12 +593,10 @@ class WiringTests extends FirrtlFlatSpec {
          |  extmodule X :
          |    input clock: Clock
          |""".stripMargin
+
     intercept[WiringException] {
-      val c = passes.foldLeft(parse(input)) {
-        (c: Circuit, p: Pass) => p.run(c)
-      }
       val wiringPass = new Wiring(Seq(sas))
-      val retC = wiringPass.run(c)
+      executeTest(input, "", passes :+ wiringPass)
     }
   }
 
@@ -666,12 +638,9 @@ class WiringTests extends FirrtlFlatSpec {
          |    input clock: Clock
          |    input pin: UInt<2>
          |""".stripMargin
-    val c = passes.foldLeft(parse(input)) {
-      (c: Circuit, p: Pass) => p.run(c)
-    }
+
     val wiringPass = new Wiring(Seq(sas))
-    val retC = wiringPass.run(c)
-    (parse(retC.serialize).serialize) should be (parse(check).serialize)
+    executeTest(input, check, passes :+ wiringPass)
   }
 
   it should "wire using Annotations with a sink module" in {
@@ -701,12 +670,9 @@ class WiringTests extends FirrtlFlatSpec {
          |    input clk: Clock
          |    input pin: UInt<5>
          |""".stripMargin
-    val c = passes.foldLeft(parse(input)) {
-      (c: Circuit, p: Pass) => p.run(c)
-    }
+
     val wiringXForm = new WiringTransform()
-    val retC = wiringXForm.execute(CircuitState(c, MidForm, Seq(source, sink))).circuit
-    (parse(retC.serialize).serialize) should be (parse(check).serialize)
+    executeTest(input, check, passes :+ wiringXForm, Seq(source, sink))
   }
 
   it should "wire using Annotations with a sink component" in {
@@ -739,12 +705,9 @@ class WiringTests extends FirrtlFlatSpec {
          |    wire s: UInt<5>
          |    s <= pin
          |""".stripMargin
-    val c = passes.foldLeft(parse(input)) {
-      (c: Circuit, p: Pass) => p.run(c)
-    }
+
     val wiringXForm = new WiringTransform()
-    val retC = wiringXForm.execute(CircuitState(c, MidForm, Seq(source, sink))).circuit
-    (parse(retC.serialize).serialize) should be (parse(check).serialize)
+    executeTest(input, check, passes :+ wiringXForm, Seq(source, sink))
   }
 
   it should "wire using annotations with Aggregate source" in {
@@ -785,12 +748,9 @@ class WiringTests extends FirrtlFlatSpec {
          |    input clock : Clock
          |    input pin : {x : UInt<1>, y: UInt<1>, z: {zz : UInt<1>} }"""
         .stripMargin
-    val c = passes.foldLeft(parse(input)) {
-      (c: Circuit, p: Pass) => p.run(c)
-    }
+
     val wiringXForm = new WiringTransform()
-    val retC = wiringXForm.execute(CircuitState(c, MidForm, Seq(source, sink))).circuit
-    (parse(retC.serialize).serialize) should be (parse(check).serialize)
+    executeTest(input, check, passes :+ wiringXForm, Seq(source, sink))
   }
 
   it should "wire one sink to multiple, disjoint extmodules" in {
@@ -845,11 +805,8 @@ class WiringTests extends FirrtlFlatSpec {
          |    input clock: Clock
          |    input pin: UInt<5>
          |""".stripMargin
-    val c = passes.foldLeft(parse(input)) {
-      (c: Circuit, p: Pass) => p.run(c)
-    }
+
     val wiringPass = new Wiring(wiSeq)
-    val retC = wiringPass.run(c)
-    (parse(retC.serialize).serialize) should be (parse(check).serialize)
+    executeTest(input, check, passes :+ wiringPass)
   }
 }