diff options
| author | Schuyler Eldridge | 2019-09-16 19:03:37 -0400 |
|---|---|---|
| committer | GitHub | 2019-09-16 19:03:37 -0400 |
| commit | f93e1d240f80848dc12c25906239fe6c8a4d42b5 (patch) | |
| tree | 9b39634fc4bd5044e37939a0bd568ae4ed158826 /src/test/scala/firrtlTests/WidthSpec.scala | |
| parent | 7e39ea8ec948ff1db7ccd0d850923a86d2d8a4e7 (diff) | |
| parent | b3dd7924f27342083681be6dd5932ef95d354029 (diff) | |
Merge pull request #1124 from freechipsproject/gender-to-flow
Gender to Flow
Diffstat (limited to 'src/test/scala/firrtlTests/WidthSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/WidthSpec.scala | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/test/scala/firrtlTests/WidthSpec.scala b/src/test/scala/firrtlTests/WidthSpec.scala index 96bd249c..4c0e7f70 100644 --- a/src/test/scala/firrtlTests/WidthSpec.scala +++ b/src/test/scala/firrtlTests/WidthSpec.scala @@ -53,7 +53,7 @@ class WidthSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, + ResolveFlows, new InferWidths, CheckWidths) val input = @@ -76,7 +76,7 @@ class WidthSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, + ResolveFlows, new InferWidths, CheckWidths) val input = @@ -95,7 +95,7 @@ class WidthSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, + ResolveFlows, new InferWidths, CheckWidths) val input = @@ -120,7 +120,7 @@ class WidthSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, + ResolveFlows, new InferWidths) val input = """circuit Unit : @@ -142,7 +142,7 @@ class WidthSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, + ResolveFlows, new InferWidths) val input = """circuit Unit : @@ -165,7 +165,7 @@ class WidthSpec extends FirrtlFlatSpec { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, + ResolveFlows, new InferWidths, CheckWidths) val input = |