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authorSchuyler Eldridge2018-11-05 16:54:42 -0500
committerGitHub2018-11-05 16:54:42 -0500
commitd04af59c233cec994087df3d0d3fff14e20ac04c (patch)
tree0b7ae45a3901986a40bf06abad24adf3ea6fe15d /src/test/scala/firrtlTests/WidthSpec.scala
parent3935914116d7289a8b545cc8d758785d9f8dcd13 (diff)
parent2fdc984223393ee4996f7f7fde8d6b12c9fe36c3 (diff)
Merge pull request #932 from seldridge/f269
- Add Target.prettyPrint method - Improve UninferredWidth exception message
Diffstat (limited to 'src/test/scala/firrtlTests/WidthSpec.scala')
-rw-r--r--src/test/scala/firrtlTests/WidthSpec.scala25
1 files changed, 25 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/WidthSpec.scala b/src/test/scala/firrtlTests/WidthSpec.scala
index ab8cb7ac..058cc1fa 100644
--- a/src/test/scala/firrtlTests/WidthSpec.scala
+++ b/src/test/scala/firrtlTests/WidthSpec.scala
@@ -156,4 +156,29 @@ class WidthSpec extends FirrtlFlatSpec {
executeTest(input, check, passes)
}
}
+
+ behavior of "CheckWidths.UniferredWidth"
+
+ it should "provide a good error message with a full target if a user forgets an assign" in {
+ val passes = Seq(
+ ToWorkingIR,
+ ResolveKinds,
+ InferTypes,
+ CheckTypes,
+ ResolveGenders,
+ InferWidths,
+ CheckWidths)
+ val input =
+ """|circuit Foo :
+ | module Foo :
+ | input clock : Clock
+ | inst bar of Bar
+ | module Bar :
+ | wire a: { b : UInt<1>, c : { d : UInt<1>, e : UInt } }
+ |""".stripMargin
+ val msg = intercept[CheckWidths.UninferredWidth] { executeTest(input, Nil, passes) }
+ .getMessage should include ("""| circuit Foo:
+ | └── module Bar:
+ | └── a.c.e""".stripMargin)
+ }
}