All of src/ formatted with scalafmt

1 files changed, 25 insertions, 28 deletions

diff --git a/src/test/scala/firrtlTests/WidthSpec.scala b/src/test/scala/firrtlTests/WidthSpec.scala
index 4b0bc5e5..b8fb3955 100644
--- a/src/test/scala/firrtlTests/WidthSpec.scala
+++ b/src/test/scala/firrtlTests/WidthSpec.scala
@@ -8,24 +8,20 @@ import firrtl.testutils._
 
 class WidthSpec extends FirrtlFlatSpec {
   private def executeTest(input: String, expected: Seq[String], passes: Seq[Transform]) = {
-    val c = passes.foldLeft(CircuitState(Parser.parse(input.split("\n").toIterator), UnknownForm)) {
-      (c: CircuitState, p: Transform) => p.runTransform(c)
-    }.circuit
-    val lines = c.serialize.split("\n") map normalized
+    val c = passes
+      .foldLeft(CircuitState(Parser.parse(input.split("\n").toIterator), UnknownForm)) {
+        (c: CircuitState, p: Transform) => p.runTransform(c)
+      }
+      .circuit
+    val lines = c.serialize.split("\n").map(normalized)
 
-    expected foreach { e =>
+    expected.foreach { e =>
       lines should contain(e)
     }
   }
 
-  private val inferPasses = Seq(
-    ToWorkingIR,
-    CheckHighForm,
-    ResolveKinds,
-    InferTypes,
-    CheckTypes,
-    ResolveFlows,
-    new InferWidths)
+  private val inferPasses =
+    Seq(ToWorkingIR, CheckHighForm, ResolveKinds, InferTypes, CheckTypes, ResolveFlows, new InferWidths)
 
   private val inferAndCheckPasses = inferPasses :+ CheckWidths
 
@@ -42,13 +38,13 @@ class WidthSpec extends FirrtlFlatSpec {
     LiteralWidthCheck(4, Some(3), 4)
   )
   for (LiteralWidthCheck(lit, uwo, sw) <- litChecks) {
-    import firrtl.ir.{UIntLiteral, SIntLiteral, IntWidth}
+    import firrtl.ir.{IntWidth, SIntLiteral, UIntLiteral}
     s"$lit" should s"have signed width $sw" in {
-      SIntLiteral(lit).width should equal (IntWidth(sw))
+      SIntLiteral(lit).width should equal(IntWidth(sw))
     }
     uwo.foreach { uw =>
       it should s"have unsigned width $uw" in {
-        UIntLiteral(lit).width should equal (IntWidth(uw))
+        UIntLiteral(lit).width should equal(IntWidth(uw))
       }
     }
   }
@@ -75,7 +71,7 @@ class WidthSpec extends FirrtlFlatSpec {
          |    input i: UInt<2>
          |    node x = asClock(i)""".stripMargin
     intercept[CheckWidths.MultiBitAsClock] {
-        executeTest(input, Nil, inferAndCheckPasses)
+      executeTest(input, Nil, inferAndCheckPasses)
     }
   }
 
@@ -86,15 +82,15 @@ class WidthSpec extends FirrtlFlatSpec {
          |    input i: UInt<2>
          |    node x = asAsyncReset(i)""".stripMargin
     intercept[CheckWidths.MultiBitAsAsyncReset] {
-        executeTest(input, Nil, inferAndCheckPasses)
+      executeTest(input, Nil, inferAndCheckPasses)
     }
   }
 
   "Width >= MaxWidth" should "result in an error" in {
     val input =
-     s"""circuit Unit :
-        |  module Unit :
-        |    input x: UInt<${CheckWidths.MaxWidth}>
+      s"""circuit Unit :
+         |  module Unit :
+         |    input x: UInt<${CheckWidths.MaxWidth}>
       """.stripMargin
     intercept[CheckWidths.WidthTooBig] {
       executeTest(input, Nil, inferAndCheckPasses)
@@ -124,7 +120,7 @@ class WidthSpec extends FirrtlFlatSpec {
         |    input y: SInt<2>
         |    output z: SInt
         |    z <= add(x, y)""".stripMargin
-    val check = Seq( "output z : SInt<4>")
+    val check = Seq("output z : SInt<4>")
     intercept[PassExceptions] {
       executeTest(input, check, inferPasses)
     }
@@ -138,13 +134,13 @@ class WidthSpec extends FirrtlFlatSpec {
         |    input y: SInt<2>
         |    output z: SInt
         |    z <= sub(y, x)""".stripMargin
-    val check = Seq( "output z : SInt<5>")
+    val check = Seq("output z : SInt<5>")
     intercept[PassExceptions] {
       executeTest(input, check, inferPasses)
     }
   }
 
-  behavior of "CheckWidths.UniferredWidth"
+  behavior.of("CheckWidths.UniferredWidth")
 
   it should "provide a good error message with a full target if a user forgets an assign" in {
     val input =
@@ -155,9 +151,10 @@ class WidthSpec extends FirrtlFlatSpec {
          |  module Bar :
          |    wire a: { b : UInt<1>, c : { d : UInt<1>, e : UInt } }
          |""".stripMargin
-    val msg = intercept[CheckWidths.UninferredWidth] { executeTest(input, Nil, inferAndCheckPasses) }
-      .getMessage should include ("""|    circuit Foo:
-                                     |    └── module Bar:
-                                     |        └── a.c.e""".stripMargin)
+    val msg = intercept[CheckWidths.UninferredWidth] {
+      executeTest(input, Nil, inferAndCheckPasses)
+    }.getMessage should include("""|    circuit Foo:
+                                   |    └── module Bar:
+                                   |        └── a.c.e""".stripMargin)
   }
 }