Merge pull request #1124 from freechipsproject/gender-to-flow

Gender to Flow

1 files changed, 16 insertions, 16 deletions

diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index 0ef4f709..b7df945f 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -95,7 +95,7 @@ class UnitTests extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
+      ResolveFlows,
       ExpandConnects)
     val input =
      """circuit Unit :
@@ -157,7 +157,7 @@ class UnitTests extends FirrtlFlatSpec {
       ToWorkingIR,
       ResolveKinds,
       InferTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       SplitExpressions
     )
@@ -181,7 +181,7 @@ class UnitTests extends FirrtlFlatSpec {
       ToWorkingIR,
       ResolveKinds,
       InferTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       PadWidths
     )
@@ -202,7 +202,7 @@ class UnitTests extends FirrtlFlatSpec {
       ToWorkingIR,
       ResolveKinds,
       InferTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       PullMuxes,
       ExpandConnects,
@@ -210,8 +210,8 @@ class UnitTests extends FirrtlFlatSpec {
       new ConstantPropagation
     )
     val input =
-      """circuit AssignViaDeref : 
-         |  module AssignViaDeref : 
+      """circuit AssignViaDeref :
+         |  module AssignViaDeref :
          |    input clock : Clock
          |    input reset : UInt<1>
          |    output io : {a : UInt<8>, sel : UInt<1>}
@@ -242,7 +242,7 @@ class UnitTests extends FirrtlFlatSpec {
       ToWorkingIR,
       ResolveKinds,
       InferTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       CheckWidths)
     val input =
@@ -261,7 +261,7 @@ class UnitTests extends FirrtlFlatSpec {
       ToWorkingIR,
       ResolveKinds,
       InferTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       CheckWidths)
     val input =
@@ -280,7 +280,7 @@ class UnitTests extends FirrtlFlatSpec {
       ToWorkingIR,
       ResolveKinds,
       InferTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       CheckWidths)
     val input =
@@ -388,12 +388,12 @@ class UnitTests extends FirrtlFlatSpec {
       ToWorkingIR,
       ResolveKinds,
       InferTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       PullMuxes,
       ExpandConnects,
       RemoveAccesses,
-      ResolveGenders,
+      ResolveFlows,
       new ConstantPropagation
     )
     val input =
@@ -412,13 +412,13 @@ class UnitTests extends FirrtlFlatSpec {
     val ut2 = UIntType(IntWidth(BigInt(2)))
     val ut1 = UIntType(IntWidth(BigInt(1)))
 
-    val mgen = WRef("_array_index", ut16, WireKind, MALE)
-    val fgen = WRef("_array_index", ut16, WireKind, FEMALE)
-    val index = WRef("index", ut2, PortKind, MALE)
-    val out = WRef("out", ut16, PortKind, FEMALE)
+    val mgen = WRef("_array_index", ut16, WireKind, SourceFlow)
+    val fgen = WRef("_array_index", ut16, WireKind, SinkFlow)
+    val index = WRef("index", ut2, PortKind, SourceFlow)
+    val out = WRef("out", ut16, PortKind, SinkFlow)
 
     def eq(e1: Expression, e2: Expression): Expression = DoPrim(PrimOps.Eq, Seq(e1, e2), Nil, ut1)
-    def array(v: Int): Expression = WSubIndex(WRef("array", VectorType(ut16, 3), WireKind, MALE), v, ut16, MALE)
+    def array(v: Int): Expression = WSubIndex(WRef("array", VectorType(ut16, 3), WireKind, SourceFlow), v, ut16, SourceFlow)
 
     result should containTree { case DefWire(_, "_array_index", `ut16`) => true }
     result should containTree { case IsInvalid(_, `fgen`) => true }