diff options
| author | Jack Koenig | 2017-06-29 14:20:09 -0700 |
|---|---|---|
| committer | GitHub | 2017-06-29 14:20:09 -0700 |
| commit | 905cac96053caf4b6c87ac0b9c8addf313d1085c (patch) | |
| tree | 7d0bcf384f63e0176acdd70f9524369bb5bb4ce0 /src/test/scala/firrtlTests/UnitTests.scala | |
| parent | 8eb69dd91e58915f8dad5e42da0a3fe686c628d8 (diff) | |
| parent | a0aeafa3d591f9bcc14eca6d8a41eb2155f1b5b0 (diff) | |
Merge pull request #617 from freechipsproject/const-prop-regs
Improvements to Constant Propagation and Testing
Diffstat (limited to 'src/test/scala/firrtlTests/UnitTests.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/UnitTests.scala | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala index 0d5d098c..f717fc18 100644 --- a/src/test/scala/firrtlTests/UnitTests.scala +++ b/src/test/scala/firrtlTests/UnitTests.scala @@ -8,13 +8,15 @@ import org.scalatest.prop._ import firrtl._ import firrtl.ir.Circuit import firrtl.passes._ +import firrtl.transforms._ import firrtl.Parser.IgnoreInfo class UnitTests extends FirrtlFlatSpec { - private def executeTest(input: String, expected: Seq[String], passes: Seq[Pass]) = { - val c = passes.foldLeft(Parser.parse(input.split("\n").toIterator)) { - (c: Circuit, p: Pass) => p.run(c) - } + private def executeTest(input: String, expected: Seq[String], transforms: Seq[Transform]) = { + val c = transforms.foldLeft(CircuitState(parse(input), UnknownForm)) { + (c: CircuitState, t: Transform) => t.runTransform(c) + }.circuit + val lines = c.serialize.split("\n") map normalized expected foreach { e => @@ -199,7 +201,7 @@ class UnitTests extends FirrtlFlatSpec { PullMuxes, ExpandConnects, RemoveAccesses, - ConstProp + new ConstantPropagation ) val input = """circuit AssignViaDeref : |
