Merge branch 'master' into update-spec

1 files changed, 2 insertions, 2 deletions

diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index cee2c15d..98693c61 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -60,7 +60,7 @@ class UnitTests extends FirrtlFlatSpec {
         |    input y: {a : UInt<1>}
         |    output x: {a : UInt<1>, b : UInt<1>}
         |    x <= y""".stripMargin
-    intercept[PassExceptions] {
+    intercept[CheckTypes.InvalidConnect] {
       passes.foldLeft(parse(input)) {
         (c: Circuit, p: Pass) => p.run(c)
       }
@@ -82,7 +82,7 @@ class UnitTests extends FirrtlFlatSpec {
        |    wire x : { valid : UInt<1> }
        |    reg y : { valid : UInt<1>, bits : UInt<3> }, clk with :
        |      reset => (reset, x)""".stripMargin
-    intercept[PassExceptions] {
+    intercept[CheckTypes.InvalidRegInit] {
       passes.foldLeft(parse(input)) {
         (c: Circuit, p: Pass) => p.run(c)
       }