diff options
| author | Jack Koenig | 2021-04-16 11:41:07 -0700 |
|---|---|---|
| committer | GitHub | 2021-04-16 11:41:07 -0700 |
| commit | bf1cf3d2db49195d031f89594baebcc9f307659e (patch) | |
| tree | 4a13e03f64c49295dc9cb620f76737d25df08419 /src/test/scala/firrtlTests/ReplSeqMemTests.scala | |
| parent | e9b2946c962f91a04611e32b1a9d03f78e7edf2b (diff) | |
Make InferTypes error on enable conditions > 1-bit wide (#2182)
Diffstat (limited to 'src/test/scala/firrtlTests/ReplSeqMemTests.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/ReplSeqMemTests.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/ReplSeqMemTests.scala b/src/test/scala/firrtlTests/ReplSeqMemTests.scala index d21f80c8..2156e392 100644 --- a/src/test/scala/firrtlTests/ReplSeqMemTests.scala +++ b/src/test/scala/firrtlTests/ReplSeqMemTests.scala @@ -422,7 +422,7 @@ circuit CustomMemory : circuit CustomMemory : module CustomMemory : input clock : Clock - output io : { flip en : UInt<1>, out : UInt<8>[2], flip raddr : UInt<10>, flip waddr : UInt<10>, flip wdata : UInt<8>[2], flip mask : UInt<8>[2] } + output io : { flip en : UInt<1>, out : UInt<8>[2], flip raddr : UInt<10>, flip waddr : UInt<10>, flip wdata : UInt<8>[2], flip mask : UInt<1>[2] } smem mem : UInt<8>[2][1024] read mport r = mem[io.raddr], clock @@ -452,7 +452,7 @@ circuit CustomMemory : circuit CustomMemory : module CustomMemory : input clock : Clock - output io : { flip en : UInt<1>, out : UInt<8>[2], flip raddr : UInt<10>, flip waddr : UInt<10>, flip wdata : UInt<8>[2], flip mask : UInt<8>[2] } + output io : { flip en : UInt<1>, out : UInt<8>[2], flip raddr : UInt<10>, flip waddr : UInt<10>, flip wdata : UInt<8>[2], flip mask : UInt<1>[2] } io.out is invalid |