diff options
| author | Colin Schmidt | 2016-10-30 14:18:48 -0700 |
|---|---|---|
| committer | Donggyu | 2016-10-30 14:18:48 -0700 |
| commit | be87c1e2481d14a2e0b68668fbfd901d3416dddd (patch) | |
| tree | c1febd7d69a3079e5459de4d62ed3f1e7f80c470 /src/test/scala/firrtlTests/ReplSeqMemTests.scala | |
| parent | 5b35f2d2722f72c81d2d6c507cd379be2a1476d8 (diff) | |
Keep package name + directory structure consistent (#354)
* Keep package name + directory structure consistent
This annoyed me so heres a PR
* fix InferReadWrite references
* delete .ConvertFixedToSInt.scala.swo
Diffstat (limited to 'src/test/scala/firrtlTests/ReplSeqMemTests.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/ReplSeqMemTests.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/ReplSeqMemTests.scala b/src/test/scala/firrtlTests/ReplSeqMemTests.scala index 277623cf..78b3d9f0 100644 --- a/src/test/scala/firrtlTests/ReplSeqMemTests.scala +++ b/src/test/scala/firrtlTests/ReplSeqMemTests.scala @@ -13,8 +13,8 @@ class ReplSeqMemSpec extends SimpleTransformSpec { new IRToWorkingIR(), new ResolveAndCheck(), new HighFirrtlToMiddleFirrtl(), - new passes.InferReadWrite(TransID(-1)), - new passes.memlib.ReplSeqMem(TransID(-2)), + new InferReadWrite(TransID(-1)), + new ReplSeqMem(TransID(-2)), new MiddleFirrtlToLowFirrtl(), (new Transform with SimpleRun { def execute(c: ir.Circuit, a: AnnotationMap) = run(c, passSeq) } ), |