diff options
| author | Kevin Laeufer | 2020-07-28 10:10:43 -0700 |
|---|---|---|
| committer | Kevin Laeufer | 2020-07-29 15:26:30 -0700 |
| commit | 093cb4993f37fccb55396abeb1a61a528f0eaa2a (patch) | |
| tree | 26488bdf8fd33e0b8693ce99c8cd119227300b76 /src/test/scala/firrtlTests/RemoveWiresSpec.scala | |
| parent | 8b66b53591703d6cded44419726b18e80d0e6bd6 (diff) | |
[2.13] toSeq, Unit -> (), and postfix fixes
Diffstat (limited to 'src/test/scala/firrtlTests/RemoveWiresSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/RemoveWiresSpec.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/RemoveWiresSpec.scala b/src/test/scala/firrtlTests/RemoveWiresSpec.scala index e6b60059..df3ceef6 100644 --- a/src/test/scala/firrtlTests/RemoveWiresSpec.scala +++ b/src/test/scala/firrtlTests/RemoveWiresSpec.scala @@ -37,7 +37,7 @@ class RemoveWiresSpec extends FirrtlFlatSpec { circuit.modules.head match { case Module(_,_,_, body) => onStmt(body) } - (nodes, wires) + (nodes.toSeq, wires.toSeq) } def orderedNames(circuit: Circuit): Seq[String] = { @@ -55,7 +55,7 @@ class RemoveWiresSpec extends FirrtlFlatSpec { circuit.modules.head match { case Module(_,_,_, body) => onStmt(body) } - names + names.toSeq } "Remove Wires" should "turn wires and their single connect into nodes" in { |
