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authorJack Koenig2019-08-13 12:09:27 +0530
committerGitHub2019-08-13 12:09:27 +0530
commitf08f8dbb3c480220f92923a7f3242fcbb644b65e (patch)
tree45cdb7543f6252ad2feb5aaf4e0e0580d3d27565 /src/test/scala/firrtlTests/ProtoBufSpec.scala
parent63e88b6e1696e2c8d6da91f6f5eb128a9d0395ae (diff)
Infer reset (#1068)
* Add abstract "Reset" which can be inferred to AsyncReset or UInt<1> * Enhance async reset initial value literal check to support aggregates
Diffstat (limited to 'src/test/scala/firrtlTests/ProtoBufSpec.scala')
-rw-r--r--src/test/scala/firrtlTests/ProtoBufSpec.scala5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/ProtoBufSpec.scala b/src/test/scala/firrtlTests/ProtoBufSpec.scala
index 526a194c..2f347c6d 100644
--- a/src/test/scala/firrtlTests/ProtoBufSpec.scala
+++ b/src/test/scala/firrtlTests/ProtoBufSpec.scala
@@ -180,4 +180,9 @@ class ProtoBufSpec extends FirrtlFlatSpec {
val port = ir.Port(ir.NoInfo, "reset", ir.Input, ir.AsyncResetType)
FromProto.convert(ToProto.convert(port).build) should equal (port)
}
+
+ it should "support ResetTypes" in {
+ val port = ir.Port(ir.NoInfo, "reset", ir.Input, ir.ResetType)
+ FromProto.convert(ToProto.convert(port).build) should equal (port)
+ }
}