diff options
| author | Jiuyang Liu | 2020-10-27 00:48:54 +0800 |
|---|---|---|
| committer | GitHub | 2020-10-27 00:48:54 +0800 |
| commit | d1c0181e716c37142e233beed2efcea5c5794aa7 (patch) | |
| tree | f396139f5dca9aace34be2cb8e9e1ccfeda1190f /src/test/scala/firrtlTests/LoweringCompilersSpec.scala | |
| parent | a5a8c7a8f5d1dd38ac3452d7c98ac7773f692304 (diff) | |
| parent | 61f3e886affce326a2c09c2f5ba8a69465c0c2ee (diff) | |
Merge pull request #1932 from freechipsproject/fix_VerilogPrep
Fix verilog prep
Diffstat (limited to 'src/test/scala/firrtlTests/LoweringCompilersSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/LoweringCompilersSpec.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala index ffaaf332..54f0af8e 100644 --- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala +++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala @@ -249,6 +249,7 @@ class LoweringCompilersSpec extends AnyFlatSpec with Matchers { new firrtl.transforms.FlattenRegUpdate, firrtl.passes.VerilogModulusCleanup, new firrtl.transforms.VerilogRename, + firrtl.passes.InferTypes, firrtl.passes.VerilogPrep, new firrtl.AddDescriptionNodes ) @@ -273,6 +274,7 @@ class LoweringCompilersSpec extends AnyFlatSpec with Matchers { new firrtl.transforms.DeadCodeElimination, firrtl.passes.VerilogModulusCleanup, new firrtl.transforms.VerilogRename, + firrtl.passes.InferTypes, firrtl.passes.VerilogPrep, new firrtl.AddDescriptionNodes ) |