InferTypes: fix bugs with unknown widths on ports and memories (#1769)

* InferTypesFlowsAndKindsSpec: test the results of InferTypes, ResolveKinds and ResolveFlows

* Don't use passes sub-package in tests

This changes two test files using the "passes" sub-package to
"firrtl.passes". This allows a new "firrtlTests.passes" package to be
freely created and used without a name collision.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* ResolveFlows: only depends on types and working ir

The types are needed to know the orientation of
a bundle field of a SubField node.

* InferTypes: fix bugs with unknown widths on ports and memories

* LoweringCompileSpec: Uniquify pass moved

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

1 files changed, 62 insertions, 56 deletions

diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
index 854763f1..ae546f7b 100644
--- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
+++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
@@ -5,7 +5,6 @@ package firrtlTests
 import org.scalatest.{FlatSpec, Matchers}
 
 import firrtl._
-import firrtl.passes
 import firrtl.options.Dependency
 import firrtl.stage.{Forms, TransformManager}
 
@@ -36,75 +35,75 @@ class LoweringCompilersSpec extends FlatSpec with Matchers {
 
   def legacyTransforms(a: CoreTransform): Seq[Transform] = a match {
     case _: ChirrtlToHighFirrtl => Seq(
-      passes.CheckChirrtl,
-      passes.CInferTypes,
-      passes.CInferMDir,
-      passes.RemoveCHIRRTL)
-    case _: IRToWorkingIR => Seq(passes.ToWorkingIR)
+      firrtl.passes.CheckChirrtl,
+      firrtl.passes.CInferTypes,
+      firrtl.passes.CInferMDir,
+      firrtl.passes.RemoveCHIRRTL)
+    case _: IRToWorkingIR => Seq(firrtl.passes.ToWorkingIR)
     case _: ResolveAndCheck => Seq(
-      passes.CheckHighForm,
-      passes.ResolveKinds,
-      passes.InferTypes,
-      passes.CheckTypes,
-      passes.Uniquify,
-      passes.ResolveKinds,
-      passes.InferTypes,
-      passes.ResolveFlows,
-      passes.CheckFlows,
-      new passes.InferBinaryPoints,
-      new passes.TrimIntervals,
-      new passes.InferWidths,
-      passes.CheckWidths,
+      firrtl.passes.CheckHighForm,
+      firrtl.passes.ResolveKinds,
+      firrtl.passes.InferTypes,
+      firrtl.passes.CheckTypes,
+      firrtl.passes.Uniquify,
+      firrtl.passes.ResolveKinds,
+      firrtl.passes.InferTypes,
+      firrtl.passes.ResolveFlows,
+      firrtl.passes.CheckFlows,
+      new firrtl.passes.InferBinaryPoints,
+      new firrtl.passes.TrimIntervals,
+      new firrtl.passes.InferWidths,
+      firrtl.passes.CheckWidths,
       new firrtl.transforms.InferResets)
     case _: HighFirrtlToMiddleFirrtl => Seq(
-      passes.PullMuxes,
-      passes.ReplaceAccesses,
-      passes.ExpandConnects,
-      passes.ZeroLengthVecs,
-      passes.RemoveAccesses,
-      passes.Uniquify,
-      passes.ExpandWhens,
-      passes.CheckInitialization,
-      passes.ResolveKinds,
-      passes.InferTypes,
-      passes.CheckTypes,
-      passes.ResolveFlows,
-      new passes.InferWidths,
-      passes.CheckWidths,
-      new passes.RemoveIntervals,
-      passes.ConvertFixedToSInt,
-      passes.ZeroWidth,
-      passes.InferTypes)
+      firrtl.passes.PullMuxes,
+      firrtl.passes.ReplaceAccesses,
+      firrtl.passes.ExpandConnects,
+      firrtl.passes.ZeroLengthVecs,
+      firrtl.passes.RemoveAccesses,
+      firrtl.passes.Uniquify,
+      firrtl.passes.ExpandWhens,
+      firrtl.passes.CheckInitialization,
+      firrtl.passes.ResolveKinds,
+      firrtl.passes.InferTypes,
+      firrtl.passes.CheckTypes,
+      firrtl.passes.ResolveFlows,
+      new firrtl.passes.InferWidths,
+      firrtl.passes.CheckWidths,
+      new firrtl.passes.RemoveIntervals,
+      firrtl.passes.ConvertFixedToSInt,
+      firrtl.passes.ZeroWidth,
+      firrtl.passes.InferTypes)
     case _: MiddleFirrtlToLowFirrtl => Seq(
-      passes.LowerTypes,
-      passes.ResolveKinds,
-      passes.InferTypes,
-      passes.ResolveFlows,
-      new passes.InferWidths,
-      passes.Legalize,
+      firrtl.passes.LowerTypes,
+      firrtl.passes.ResolveKinds,
+      firrtl.passes.InferTypes,
+      firrtl.passes.ResolveFlows,
+      new firrtl.passes.InferWidths,
+      firrtl.passes.Legalize,
       firrtl.transforms.RemoveReset,
-      passes.ResolveFlows,
+      firrtl.passes.ResolveFlows,
       new firrtl.transforms.CheckCombLoops,
       new checks.CheckResets,
       new firrtl.transforms.RemoveWires)
     case _: LowFirrtlOptimization => Seq(
-      passes.RemoveValidIf,
+      firrtl.passes.RemoveValidIf,
       new firrtl.transforms.ConstantPropagation,
-      passes.PadWidths,
+      firrtl.passes.PadWidths,
       new firrtl.transforms.ConstantPropagation,
-      passes.Legalize,
-      passes.memlib.VerilogMemDelays, // TODO move to Verilog emitter
+      firrtl.passes.Legalize,
+      firrtl.passes.memlib.VerilogMemDelays, // TODO move to Verilog emitter
       new firrtl.transforms.ConstantPropagation,
-      passes.SplitExpressions,
+      firrtl.passes.SplitExpressions,
       new firrtl.transforms.CombineCats,
-      passes.CommonSubexpressionElimination,
+      firrtl.passes.CommonSubexpressionElimination,
       new firrtl.transforms.DeadCodeElimination)
     case _: MinimumLowFirrtlOptimization => Seq(
-      passes.RemoveValidIf,
-      passes.PadWidths,
-      passes.Legalize,
-      passes.memlib.VerilogMemDelays, // TODO move to Verilog emitter
-      passes.SplitExpressions)
+      firrtl.passes.RemoveValidIf,
+      firrtl.passes.PadWidths,
+      firrtl.passes.Legalize,
+      firrtl.passes.memlib.VerilogMemDelays, // TODO move to Verilog emitter
+      firrtl.passes.SplitExpressions)
   }
 
   def compare(a: Seq[Transform], b: TransformManager, patches: Seq[PatchAction] = Seq.empty): Unit = {
@@ -147,6 +146,12 @@ class LoweringCompilersSpec extends FlatSpec with Matchers {
   it should "replicate the old order" in {
     val tm = new TransformManager(Forms.Resolved, Forms.WorkingIR)
     val patches = Seq(
+      // ResolveFlows no longer depends in Uniquify (ResolveKinds and InferTypes are fixup passes that get moved as well)
+      Del(5), Del(6), Del(7),
+      // Uniquify now is run before InferBinary Points which claims to need Uniquify
+      Add(9, Seq(Dependency(firrtl.passes.Uniquify),
+                 Dependency(firrtl.passes.ResolveKinds),
+                 Dependency(firrtl.passes.InferTypes))),
       Add(14, Seq(Dependency.fromTransform(firrtl.passes.CheckTypes)))
     )
     compare(legacyTransforms(new ResolveAndCheck), tm, patches)
@@ -164,7 +169,8 @@ class LoweringCompilersSpec extends FlatSpec with Matchers {
                  Dependency(firrtl.passes.ResolveFlows))),
       Del(7),
       Del(8),
-      Add(7, Seq(Dependency[firrtl.passes.ExpandWhensAndCheck])),
+      Add(7, Seq(Dependency(firrtl.passes.ResolveKinds),
+                 Dependency[firrtl.passes.ExpandWhensAndCheck])),
       Del(11),
       Del(12),
       Del(13),