Fix dynamic SubAccess of zero-length vectors (#1450)

* Fix dynamic SubAccess of zero-length vectors

* Fixes #230
* Add new ZeroLengthVecs pass that occurs before RemoveAccesses
* Include this in stage.Forms.MidForm
* Add to High->Mid order in compiler test based on @seldridge feedback

* Use validif to produce out-of-bounds value in ZeroLengthVecs

* Update scaladoc

* Fix test imports

1 files changed, 7 insertions, 6 deletions

diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
index dcc4e48d..648e45cd 100644
--- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
+++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
@@ -61,6 +61,7 @@ class LoweringCompilersSpec extends FlatSpec with Matchers {
       passes.PullMuxes,
       passes.ReplaceAccesses,
       passes.ExpandConnects,
+      passes.ZeroLengthVecs,
       passes.RemoveAccesses,
       passes.Uniquify,
       passes.ExpandWhens,
@@ -156,17 +157,17 @@ class LoweringCompilersSpec extends FlatSpec with Matchers {
   it should "replicate the old order" in {
     val tm = new TransformManager(Forms.MidForm, Forms.Deduped)
     val patches = Seq(
-      Add(5, Seq(Dependency(firrtl.passes.ResolveKinds),
+      Add(6, Seq(Dependency(firrtl.passes.ResolveKinds),
                  Dependency(firrtl.passes.InferTypes))),
-      Del(6),
       Del(7),
-      Add(6, Seq(Dependency[firrtl.passes.ExpandWhensAndCheck])),
-      Del(10),
+      Del(8),
+      Add(7, Seq(Dependency[firrtl.passes.ExpandWhensAndCheck])),
       Del(11),
       Del(12),
-      Add(11, Seq(Dependency(firrtl.passes.ResolveFlows),
+      Del(13),
+      Add(12, Seq(Dependency(firrtl.passes.ResolveFlows),
                   Dependency[firrtl.passes.InferWidths])),
-      Del(13)
+      Del(14)
     )
     compare(legacyTransforms(new HighFirrtlToMiddleFirrtl), tm, patches)
   }