Allow Side Effecting Statement to have Names (#2057)

* firrtl: add optional statement labels for stop, printf, assert, assume and cover

* test: parsing of statement labels

* ir: ensure that name is properly retained

* SymbolTable: add support for labled statements

* test: parsing statement labels

* test: lower types name collisions with named statements

* ignore empty names

* Inline: deal with named and unnamed statements

* RemoveWires: treat stop, printf and verification statements as "others"

* test: fix InlineInstance tests

* DeadCodeEliminations: statements are now als declarations

* CheckHighForm: ensure that statement names are not used as references

* CheckSpec: throw error if statement name collides

* add pass to automatically add missing statement names

* check: make sure that two statements cannot have the same name

* stmtLabel -> stmtName

* scalafmt

* add statement names to spec

* spec: meta data -> metadata

* EnsureStatementNames: explain naming algorithm

* remove returns

* better namespace use

* ir: add CanBeReferenced trait

* ir: add newline as jack requested

1 files changed, 54 insertions, 0 deletions

diff --git a/src/test/scala/firrtlTests/InlineInstancesTests.scala b/src/test/scala/firrtlTests/InlineInstancesTests.scala
index 6bee2b77..cc7257d2 100644
--- a/src/test/scala/firrtlTests/InlineInstancesTests.scala
+++ b/src/test/scala/firrtlTests/InlineInstancesTests.scala
@@ -460,6 +460,60 @@ class InlineInstancesTests extends LowTransformSpec {
     )
   }
 
+  "inlining named statements" should "work" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    input clock : Clock
+        |    input a : UInt<32>
+        |    output b : UInt<32>
+        |    inst i of Inline
+        |    i.clock <= clock
+        |    i.a <= a
+        |    b <= i.b
+        |  module Inline :
+        |    input clock : Clock
+        |    input a : UInt<32>
+        |    output b : UInt<32>
+        |    b <= a
+        |    assert(clock, UInt(1), eq(a,b), "a == b") : assert1
+        |    assert(clock, UInt(1), not(eq(a,b)), "a != b")
+        |    stop(clock, UInt(0), 0)
+        |""".stripMargin
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    input clock : Clock
+        |    input a : UInt<32>
+        |    output b : UInt<32>
+        |    wire i_clock : Clock
+        |    wire i_a : UInt<32>
+        |    wire i_b : UInt<32>
+        |    i_b <= i_a
+        |    assert(i_clock, UInt(1), eq(i_a, i_b), "a == b") : i_assert1
+        |    assert(i_clock, UInt(1), not(eq(i_a, i_b)), "a != b")
+        |    stop(i_clock, UInt(0), 0)
+        |    b <= i_b
+        |    i_clock <= clock
+        |    i_a <= a
+        |""".stripMargin
+    val top = CircuitTarget("Top").module("Top")
+    val inlined = top.instOf("i", "Inline")
+
+    executeWithAnnos(
+      input,
+      check,
+      Seq(
+        inline("Inline"),
+        NoCircuitDedupAnnotation,
+        DummyAnno(inlined.ref("assert1"))
+      ),
+      Seq(
+        DummyAnno(top.ref("i_assert1"))
+      )
+    )
+  }
+
   "inlining both grandparent and grandchild" should "should work" in {
     val input =
       """circuit Top :