diff options
| author | Albert Magyar | 2021-04-05 14:26:34 -0700 |
|---|---|---|
| committer | GitHub | 2021-04-05 14:26:34 -0700 |
| commit | ed5e03f960d89c8b5c999e030b2ae4586fa4a976 (patch) | |
| tree | e67a43a77c4c0fe4b729705d2c725c9e0c11943f /src/test/scala/firrtlTests/InfoSpec.scala | |
| parent | ca8b670eac0b0def66249738e52ef8137d30a8b5 (diff) | |
| parent | 1afa3b40f78d781ca1f242b49ca3a56d6cbc57e4 (diff) | |
Merge pull request #2111 from chipsalliance/fpga-backend
Add -fpga flag to enable FPGA-oriented compilation strategies (currently for memories)
Diffstat (limited to 'src/test/scala/firrtlTests/InfoSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/InfoSpec.scala | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/test/scala/firrtlTests/InfoSpec.scala b/src/test/scala/firrtlTests/InfoSpec.scala index 43fb6ee1..db4828f6 100644 --- a/src/test/scala/firrtlTests/InfoSpec.scala +++ b/src/test/scala/firrtlTests/InfoSpec.scala @@ -91,11 +91,11 @@ class InfoSpec extends FirrtlFlatSpec with FirrtlMatchers { result should containTree { case DefMemory(Info1, "m", _, _, _, _, _, _, _, _) => true } result should containLine(s"reg [7:0] m [0:31]; //$Info1") result should containLine(s"wire [7:0] m_r_data; //$Info1") - result should containLine(s"wire [4:0] m_r_addr; //$Info1") - result should containLine(s"wire [7:0] m_w_data; //$Info1") - result should containLine(s"wire [4:0] m_w_addr; //$Info1") - result should containLine(s"wire m_w_mask; //$Info1") - result should containLine(s"wire m_w_en; //$Info1") + result should containLine(s"wire [4:0] m_r_addr = addr; //$Info1") + result should containLine(s"wire [7:0] m_w_data = 8'h0; //$Info1") + result should containLine(s"wire [4:0] m_w_addr = addr; //$Info1") + result should containLine(s"wire m_w_mask = 1'h0; //$Info1") + result should containLine(s"wire m_w_en = 1'h0; //$Info1") result should containLine(s"assign m_r_data = m[m_r_addr]; //$Info1") result should containLine(s"m[m_w_addr] <= m_w_data; //$Info1") } |