consolidated wire+assign to just wire, with expression inlined (#1600)

* consolidated wire <type> x; assign x = y; to wire <type> x = y;

* Remove dead code from Emitter.scala

Co-authored-by: Albert Magyar <albert.magyar@gmail.com>

1 files changed, 2 insertions, 3 deletions

diff --git a/src/test/scala/firrtlTests/InfoSpec.scala b/src/test/scala/firrtlTests/InfoSpec.scala
index 12ba9151..48567d69 100644
--- a/src/test/scala/firrtlTests/InfoSpec.scala
+++ b/src/test/scala/firrtlTests/InfoSpec.scala
@@ -62,10 +62,9 @@ class InfoSpec extends FirrtlFlatSpec with FirrtlMatchers {
     result should containTree { case DefRegister(Info1, "r", _,_,_,_) => true }
     result should containLine (s"reg [7:0] r; //$Info1")
     result should containTree { case DefNode(Info2, "w", _) => true }
-    result should containLine (s"wire [7:0] w; //$Info2") // Node "w" declaration in Verilog
+    result should containLine (s"wire [7:0] w = x & r; //$Info2") // Node "w" declaration in Verilog
     result should containTree { case DefNode(Info3, "n", _) => true }
-    result should containLine (s"wire [7:0] n; //$Info3")
-    result should containLine (s"assign n = w | x; //$Info3")
+    result should containLine (s"wire [7:0] n = w | x; //$Info3")
   }
 
   it should "be propagated on memories" in {