diff options
| author | Albert Chen | 2018-11-15 08:53:16 -0800 |
|---|---|---|
| committer | Schuyler Eldridge | 2018-11-15 08:53:16 -0800 |
| commit | b90589f5cd9d4048ada2a05d5225874791546170 (patch) | |
| tree | 126699d5955746ecb7e4d5432299c648ec3446d5 /src/test/scala/firrtlTests/FirrtlSpec.scala | |
| parent | 6ece732d09b8610ae50545dab312d6759ac2f8e2 (diff) | |
Combine cats (#851)
- Add firrtl.transforms.CombineCats
- Use CombineCats in LowFirrtlOptimization
- Modify Verilog emitter to allow for nested Cat DoPrims
- Modify firrtlEquivalenceTest to write input FIRRTL string to test directory
Diffstat (limited to 'src/test/scala/firrtlTests/FirrtlSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/FirrtlSpec.scala | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/FirrtlSpec.scala b/src/test/scala/firrtlTests/FirrtlSpec.scala index 95b09d93..88238785 100644 --- a/src/test/scala/firrtlTests/FirrtlSpec.scala +++ b/src/test/scala/firrtlTests/FirrtlSpec.scala @@ -59,6 +59,9 @@ trait FirrtlRunners extends BackendCompilationUtilities { val compiler = new MinimumVerilogCompiler val prefix = circuit.main val testDir = createTestDirectory(prefix + "_equivalence_test") + val firrtlWriter = new PrintWriter(s"${testDir.getAbsolutePath}/$prefix.fir") + firrtlWriter.write(input) + firrtlWriter.close() val customVerilog = compiler.compileAndEmit(CircuitState(circuit, HighForm, customAnnotations), new GetNamespace +: new RenameTop(s"${prefix}_custom") +: customTransforms) |