aboutsummaryrefslogtreecommitdiff
path: root/src/test/scala/firrtlTests/FirrtlSpec.scala
diff options
context:
space:
mode:
authorjackkoenig2016-10-20 00:19:01 -0700
committerJack Koenig2016-11-04 13:29:09 -0700
commit8fa9429a6e916ab2a789f5d81fa803b022805b52 (patch)
treefac2efcbd0a68bfb1916f09afc7f003c7a3d6528 /src/test/scala/firrtlTests/FirrtlSpec.scala
parent62133264a788f46b319ebab9c31424b7e0536101 (diff)
Refactor Compilers and Transforms
* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers * Transforms define inputForm and outputForm * Custom transforms can be inserted at runtime into compiler or the Driver * Current "built-in" custom transforms handled via above mechanism * Verilog-specific passes moved to the Verilog emitter
Diffstat (limited to 'src/test/scala/firrtlTests/FirrtlSpec.scala')
-rw-r--r--src/test/scala/firrtlTests/FirrtlSpec.scala7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/FirrtlSpec.scala b/src/test/scala/firrtlTests/FirrtlSpec.scala
index f491b0f5..83cccf3b 100644
--- a/src/test/scala/firrtlTests/FirrtlSpec.scala
+++ b/src/test/scala/firrtlTests/FirrtlSpec.scala
@@ -36,6 +36,7 @@ import org.scalatest.prop._
import scala.io.Source
import firrtl._
+import firrtl.Parser.IgnoreInfo
import firrtl.Annotations.AnnotationMap
// This trait is borrowed from Chisel3, ideally this code should only exist in one location
@@ -131,6 +132,7 @@ trait BackendCompilationUtilities {
}
trait FirrtlRunners extends BackendCompilationUtilities {
+ def parse(str: String) = Parser.parse(str.split("\n").toIterator, IgnoreInfo)
lazy val cppHarness = new File(s"/top.cpp")
/** Compile a Firrtl file
*
@@ -141,6 +143,7 @@ trait FirrtlRunners extends BackendCompilationUtilities {
def compileFirrtlTest(
prefix: String,
srcDir: String,
+ customTransforms: Seq[Transform] = Seq.empty,
annotations: AnnotationMap = new AnnotationMap(Seq.empty)): File = {
val testDir = createTempDirectory(prefix)
copyResourceToFile(s"${srcDir}/${prefix}.fir", new File(testDir, s"${prefix}.fir"))
@@ -150,6 +153,7 @@ trait FirrtlRunners extends BackendCompilationUtilities {
s"$testDir/$prefix.v",
new VerilogCompiler(),
Parser.IgnoreInfo,
+ customTransforms,
annotations)
testDir
}
@@ -164,8 +168,9 @@ trait FirrtlRunners extends BackendCompilationUtilities {
prefix: String,
srcDir: String,
verilogPrefixes: Seq[String] = Seq.empty,
+ customTransforms: Seq[Transform] = Seq.empty,
annotations: AnnotationMap = new AnnotationMap(Seq.empty)) = {
- val testDir = compileFirrtlTest(prefix, srcDir, annotations)
+ val testDir = compileFirrtlTest(prefix, srcDir, customTransforms, annotations)
val harness = new File(testDir, s"top.cpp")
copyResourceToFile(cppHarness.toString, harness)