Constant prop add (#849)

* add FoldADD to const prop, add yosys miter tests

* add option for verilog compiler without optimizations

* rename FoldLogicalOp to FoldCommutativeOp

* add GetNamespace and RenameModules, GetNamespace stores namespace as a ModuleNamespaceAnnotation

* add constant propagation for Tail DoPrims

* add scaladocs for MinimumLowFirrtlOptimization and yosysExpectFalure/Success, add constant propagation for Head DoPrim

* add legalize pass to MinimumLowFirrtlOptimizations, use constPropBitExtract in legalize pass

1 files changed, 60 insertions, 5 deletions

diff --git a/src/test/scala/firrtlTests/FirrtlSpec.scala b/src/test/scala/firrtlTests/FirrtlSpec.scala
index 01ae0431..95b09d93 100644
--- a/src/test/scala/firrtlTests/FirrtlSpec.scala
+++ b/src/test/scala/firrtlTests/FirrtlSpec.scala
@@ -5,22 +5,79 @@ package firrtlTests
 import java.io._
 
 import com.typesafe.scalalogging.LazyLogging
+
 import scala.sys.process._
 import org.scalatest._
 import org.scalatest.prop._
-import scala.io.Source
 
+import scala.io.Source
 import firrtl._
 import firrtl.ir._
-import firrtl.Parser.UseInfo
+import firrtl.Parser.{IgnoreInfo, UseInfo}
+import firrtl.analyses.{GetNamespace, InstanceGraph, ModuleNamespaceAnnotation}
 import firrtl.annotations._
-import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation}
+import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation, RenameModules}
 import firrtl.util.BackendCompilationUtilities
 
+import scala.collection.mutable
+
 trait FirrtlRunners extends BackendCompilationUtilities {
 
   val cppHarnessResourceName: String = "/firrtl/testTop.cpp"
 
+  private class RenameTop(newTopPrefix: String) extends Transform {
+    def inputForm: LowForm.type = LowForm
+    def outputForm: LowForm.type = LowForm
+
+    def execute(state: CircuitState): CircuitState = {
+      val namespace = state.annotations.collectFirst {
+        case m: ModuleNamespaceAnnotation => m
+      }.get.namespace
+
+      val newTopName = namespace.newName(newTopPrefix)
+      val modulesx = state.circuit.modules.map {
+        case mod: Module if mod.name == state.circuit.main => mod.mapString(_ => newTopName)
+        case other => other
+      }
+
+      state.copy(circuit = state.circuit.copy(main = newTopName, modules = modulesx))
+    }
+  }
+
+  /** Check equivalence of Firrtl transforms using yosys
+    *
+    * @param input string containing Firrtl source
+    * @param customTransforms Firrtl transforms to test for equivalence
+    * @param customAnnotations Optional Firrtl annotations
+    * @param resets tell yosys which signals to set for SAT, format is (timestep, signal, value)
+    */
+  def firrtlEquivalenceTest(input: String,
+                            customTransforms: Seq[Transform] = Seq.empty,
+                            customAnnotations: AnnotationSeq = Seq.empty,
+                            resets: Seq[(Int, String, Int)] = Seq.empty): Unit = {
+    val circuit = Parser.parse(input.split("\n").toIterator)
+    val compiler = new MinimumVerilogCompiler
+    val prefix = circuit.main
+    val testDir = createTestDirectory(prefix + "_equivalence_test")
+
+    val customVerilog = compiler.compileAndEmit(CircuitState(circuit, HighForm, customAnnotations),
+      new GetNamespace +: new RenameTop(s"${prefix}_custom") +: customTransforms)
+    val namespaceAnnotation = customVerilog.annotations.collectFirst { case m: ModuleNamespaceAnnotation => m }.get
+    val customTop = customVerilog.circuit.main
+    val customFile = new PrintWriter(s"${testDir.getAbsolutePath}/$customTop.v")
+    customFile.write(customVerilog.getEmittedCircuit.value)
+    customFile.close()
+
+    val referenceVerilog = compiler.compileAndEmit(CircuitState(circuit, HighForm, Seq(namespaceAnnotation)),
+      Seq(new RenameModules, new RenameTop(s"${prefix}_reference")))
+    val referenceTop = referenceVerilog.circuit.main
+    val referenceFile = new PrintWriter(s"${testDir.getAbsolutePath}/$referenceTop.v")
+    referenceFile.write(referenceVerilog.getEmittedCircuit.value)
+    referenceFile.close()
+
+    assert(yosysExpectSuccess(customTop, referenceTop, testDir, resets))
+  }
+
   /** Compiles input Firrtl to Verilog */
   def compileToVerilog(input: String, annotations: AnnotationSeq = Seq.empty): String = {
     val circuit = Parser.parse(input.split("\n").toIterator)
@@ -248,5 +305,3 @@ abstract class CompilationTest(name: String, dir: String) extends FirrtlPropSpec
     compileFirrtlTest(name, dir)
   }
 }
-
-