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authorAdam Izraelevitz2017-05-10 11:23:18 -0700
committerGitHub2017-05-10 11:23:18 -0700
commit8b8eb4eac5b353d4d632065c78faf6a706d6aae8 (patch)
tree39e2d9344166b61b376df9d3cd15a4787bcd01f4 /src/test/scala/firrtlTests/ExpandWhensSpec.scala
parentaf222c1737fa72fce964190876346bdb7ff220cd (diff)
Update rename2 (#478)
* Added pass name to debug logger * Addresses #459. Rewords transform annotations API. Now, any annotation not propagated by a transform is considered deleted. A new DeletedAnnotation is added in place of it. * Added more stylized debugging style * WIP: make pass transform * WIP: All tests pass, need to pull master * Cleaned up PR * Added rename updates to all core transforms * Added more rename tests, and bugfixes * Renaming tracks non-leaf subfields E.g. given: wire x: {a: UInt<1>, b: UInt<1>[2]} Annotating x.b will eventually annotate x_b_0 and x_b_1 * Bugfix instance rename lowering broken * Address review comments * Remove check for seqTransform, UnknownForm too restrictive check
Diffstat (limited to 'src/test/scala/firrtlTests/ExpandWhensSpec.scala')
-rw-r--r--src/test/scala/firrtlTests/ExpandWhensSpec.scala16
1 files changed, 9 insertions, 7 deletions
diff --git a/src/test/scala/firrtlTests/ExpandWhensSpec.scala b/src/test/scala/firrtlTests/ExpandWhensSpec.scala
index a7824087..dcaf52e3 100644
--- a/src/test/scala/firrtlTests/ExpandWhensSpec.scala
+++ b/src/test/scala/firrtlTests/ExpandWhensSpec.scala
@@ -11,10 +11,12 @@ import firrtl.ir._
import firrtl.Parser.IgnoreInfo
class ExpandWhensSpec extends FirrtlFlatSpec {
- private def executeTest(input: String, check: String, passes: Seq[Pass], expected: Boolean) = {
- val c = passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
- (c: Circuit, p: Pass) => p.run(c)
+ private def executeTest(input: String, check: String, transforms: Seq[Transform], expected: Boolean) = {
+ val circuit = Parser.parse(input.split("\n").toIterator)
+ val result = transforms.foldLeft(CircuitState(circuit, UnknownForm)) {
+ (c: CircuitState, p: Transform) => p.runTransform(c)
}
+ val c = result.circuit
val lines = c.serialize.split("\n") map normalized
println(c.serialize)
@@ -25,7 +27,7 @@ class ExpandWhensSpec extends FirrtlFlatSpec {
}
}
"Expand Whens" should "not emit INVALID" in {
- val passes = Seq(
+ val transforms = Seq(
ToWorkingIR,
CheckHighForm,
ResolveKinds,
@@ -51,10 +53,10 @@ class ExpandWhensSpec extends FirrtlFlatSpec {
| a is invalid
| a.b <= UInt<64>("h04000000000000000")""".stripMargin
val check = "INVALID"
- executeTest(input, check, passes, false)
+ executeTest(input, check, transforms, false)
}
"Expand Whens" should "void unwritten memory fields" in {
- val passes = Seq(
+ val transforms = Seq(
ToWorkingIR,
CheckHighForm,
ResolveKinds,
@@ -92,7 +94,7 @@ class ExpandWhensSpec extends FirrtlFlatSpec {
| memory.w0.clk <= clk
| """.stripMargin
val check = "VOID"
- executeTest(input, check, passes, true)
+ executeTest(input, check, transforms, true)
}
}