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authorTom Alcorn2020-06-23 13:12:05 -0700
committerGitHub2020-06-23 13:12:05 -0700
commit8322316a2f7c7fe7dad72f413e75d6b4600823f0 (patch)
treedb69527225ce78a9c33be6844c7836428d1f3af7 /src/test/scala/firrtlTests/ExpandWhensSpec.scala
parentd1db9067309fe2d7765def39ac4085edfe53d7be (diff)
Basic model checking API (#1653)
* Add assume, assert, cover statements * Assert submodule assumptions * Add warning when removing verification statements * Remove System Verilog behaviour emitter warning * Add option to disable AssertSubmoduleAssumptions * Document verification statements in the spec The syntax for the new statements is assert(clk, cond, en, msg) assume(clk, cond, en, msg) cover(clk, cond, en, msg) With assert as a representative example, the semantics is as follows: `clk` is the clock, `cond` is the expression being asserted, `en` is the enable signal (if `en` is low then the assert is not checked) and `msg` is a string message intended to be reported as an error message by the model checker if the assertion fails. In the Verilog emitter, the new statements are handled by a new `formals` map, which groups the statements by clock domain. All model checking statements are then emitted within the context of an `ifdef FORMAL` block, which allows model checking tools (like Symbiyosys) to utilize the statements while keeping them out of synthesis flows. Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Diffstat (limited to 'src/test/scala/firrtlTests/ExpandWhensSpec.scala')
-rw-r--r--src/test/scala/firrtlTests/ExpandWhensSpec.scala14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/ExpandWhensSpec.scala b/src/test/scala/firrtlTests/ExpandWhensSpec.scala
index d4b3d0df..250a75d7 100644
--- a/src/test/scala/firrtlTests/ExpandWhensSpec.scala
+++ b/src/test/scala/firrtlTests/ExpandWhensSpec.scala
@@ -134,6 +134,20 @@ class ExpandWhensSpec extends FirrtlFlatSpec {
val check = "mux(p, in[0], in[1])"
executeTest(input, check, true)
}
+ it should "handle asserts" in {
+ val input =
+ """circuit Test :
+ | module Test :
+ | input clock : Clock
+ | input in : UInt<32>
+ | input p : UInt<1>
+ | when p :
+ | assert(clock, eq(in, UInt<1>("h1")), UInt<1>("h1"), "assert0")
+ | else :
+ | skip""".stripMargin
+ val check = "assert(clock, eq(in, UInt<1>(\"h1\")), and(and(UInt<1>(\"h1\"), p), UInt<1>(\"h1\")), \"assert0\")"
+ executeTest(input, check, true)
+ }
}
class ExpandWhensExecutionTest extends ExecutionTest("ExpandWhens", "/passes/ExpandWhens")