diff options
| author | Jack Koenig | 2017-11-09 19:02:43 -0800 |
|---|---|---|
| committer | Jack Koenig | 2017-12-12 15:34:43 -0800 |
| commit | e39609a2bfbbd108fa1e5044e9c270685d75a816 (patch) | |
| tree | 3f773ec4197c4a2ec9969c6e75db16afffe57f51 /src/test/scala/firrtlTests/DCETests.scala | |
| parent | 7cc075438aa8b67fb52f0556ac9a5bc07bcca232 (diff) | |
Add RemoveWires transform
This transform replaces all wires with nodes in a legal, flow-forward
order
Diffstat (limited to 'src/test/scala/firrtlTests/DCETests.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/DCETests.scala | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/test/scala/firrtlTests/DCETests.scala b/src/test/scala/firrtlTests/DCETests.scala index ea34d4be..d1848ab8 100644 --- a/src/test/scala/firrtlTests/DCETests.scala +++ b/src/test/scala/firrtlTests/DCETests.scala @@ -60,9 +60,8 @@ class DCETests extends FirrtlFlatSpec { | module Top : | input x : UInt<1> | output z : UInt<1> - | wire a : UInt<1> - | z <= x - | a <= x""".stripMargin + | node a = x + | z <= x""".stripMargin exec(input, check, Seq(dontTouch("Top.a"))) } "Unread register" should "be deleted" in { |