diff options
| author | Murali Vijayaraghavan | 2020-05-13 09:47:47 -0700 |
|---|---|---|
| committer | GitHub | 2020-05-13 16:47:47 +0000 |
| commit | 96fbaf5025ab337a6fc151795f49c1891f79a91e (patch) | |
| tree | c8b0cde148815fc438891ac0c1d684de56475a47 /src/test/scala/firrtlTests/DCETests.scala | |
| parent | d7631649488d24b5edbbb8c8de251f8e652f6304 (diff) | |
consolidated wire+assign to just wire, with expression inlined (#1600)
* consolidated wire <type> x; assign x = y; to wire <type> x = y;
* Remove dead code from Emitter.scala
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Diffstat (limited to 'src/test/scala/firrtlTests/DCETests.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/DCETests.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/DCETests.scala b/src/test/scala/firrtlTests/DCETests.scala index f03cd8db..b309467a 100644 --- a/src/test/scala/firrtlTests/DCETests.scala +++ b/src/test/scala/firrtlTests/DCETests.scala @@ -502,7 +502,7 @@ class DCECommandLineSpec extends FirrtlFlatSpec { "Dead Code Elimination" should "run by default" in { firrtl.Driver.execute(args) match { case FirrtlExecutionSuccess(_, verilog) => - verilog should not include regex ("wire +a;") + verilog should not include regex ("wire +a") case _ => fail("Unexpected compilation failure") } } @@ -510,7 +510,7 @@ class DCECommandLineSpec extends FirrtlFlatSpec { it should "not run when given --no-dce option" in { firrtl.Driver.execute(args :+ "--no-dce") match { case FirrtlExecutionSuccess(_, verilog) => - verilog should include regex ("wire +a;") + verilog should include regex ("wire +a") case _ => fail("Unexpected compilation failure") } } |
