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authorDavid Biancolin2020-03-09 17:53:11 -0700
committerGitHub2020-03-09 17:53:11 -0700
commit113a4aa3641c49b4c86e0cc23b3897b935c9b445 (patch)
treedc991d77b3a1c6328d60bc98add2cc0d2ed70451 /src/test/scala/firrtlTests/DCETests.scala
parent0c40f2b3bf0088a226cdfcb551fc72972a030395 (diff)
Provide an annotation mix-in that marks RTs as dontTouch (#1433)
* Provide an annotation mix-in that marks RTs as dontTouch * Update src/main/scala/firrtl/transforms/OptimizationAnnotations.scala Co-Authored-By: Albert Magyar <albert.magyar@gmail.com> * Update src/test/scala/firrtlTests/DCETests.scala Co-Authored-By: Albert Magyar <albert.magyar@gmail.com> * Update src/main/scala/firrtl/transforms/OptimizationAnnotations.scala * Update OptimizationAnnotations.scala Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Diffstat (limited to 'src/test/scala/firrtlTests/DCETests.scala')
-rw-r--r--src/test/scala/firrtlTests/DCETests.scala25
1 files changed, 25 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/DCETests.scala b/src/test/scala/firrtlTests/DCETests.scala
index a9dbdda2..bfd47042 100644
--- a/src/test/scala/firrtlTests/DCETests.scala
+++ b/src/test/scala/firrtlTests/DCETests.scala
@@ -11,6 +11,13 @@ import firrtl.passes.memlib.SimpleTransform
import java.io.File
import java.nio.file.Paths
+case class AnnotationWithDontTouches(target: ReferenceTarget)
+ extends SingleTargetAnnotation[ReferenceTarget] with HasDontTouches {
+ def targets = Seq(target)
+ def duplicate(n: ReferenceTarget) = this.copy(n)
+ def dontTouches: Seq[ReferenceTarget] = targets
+}
+
class DCETests extends FirrtlFlatSpec {
// Not using executeTest because it is for positive testing, we need to check that stuff got
// deleted
@@ -63,6 +70,24 @@ class DCETests extends FirrtlFlatSpec {
| z <= x""".stripMargin
exec(input, check, Seq(dontTouch("Top.a")))
}
+ "Unread wire marked dont touch by another annotation" should "NOT be deleted" in {
+ val input =
+ """circuit Top :
+ | module Top :
+ | input x : UInt<1>
+ | output z : UInt<1>
+ | wire a : UInt<1>
+ | z <= x
+ | a <= x""".stripMargin
+ val check =
+ """circuit Top :
+ | module Top :
+ | input x : UInt<1>
+ | output z : UInt<1>
+ | node a = x
+ | z <= x""".stripMargin
+ exec(input, check, Seq(AnnotationWithDontTouches(ModuleTarget("Top", "Top").ref("a"))))
+ }
"Unread register" should "be deleted" in {
val input =
"""circuit Top :