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authorJack Koenig2020-09-14 19:43:01 -0700
committerGitHub2020-09-15 02:43:01 +0000
commit0c646459b52394e8a388143cee324b8af3dc7c09 (patch)
tree2a346a8669a48ae8ddba72488686f5cc70e98383 /src/test/scala/firrtlTests/DCETests.scala
parent5f410f0e4774121932d644f31fde83b9b8ed78be (diff)
Don't use ResolvedAnnotationPaths in ConstProp nor DCE (#1896)
Both use EliminateTargetPaths to duplicate modules based on annotations. Currently, EliminateTargetPaths API is a little too limited so it duplicates more than it should which effectively breaks Dedup whenever DontTouchAnnotations are present. Also, make ConstProp and DCE treat all HasDontTouches as local annotations even if they are instance annotations. This is more conservative but it is generally better to preserve deduplication than to maximally optimize every instance. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'src/test/scala/firrtlTests/DCETests.scala')
-rw-r--r--src/test/scala/firrtlTests/DCETests.scala36
1 files changed, 36 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/DCETests.scala b/src/test/scala/firrtlTests/DCETests.scala
index a9084f0b..f1c0001a 100644
--- a/src/test/scala/firrtlTests/DCETests.scala
+++ b/src/test/scala/firrtlTests/DCETests.scala
@@ -491,6 +491,42 @@ class DCETests extends FirrtlFlatSpec {
(verilog shouldNot include).regex("""fwrite""")
(verilog shouldNot include).regex("""fatal""")
}
+
+ "DCE" should "not duplicate unnecessarily" in {
+ val input =
+ """circuit Top :
+ | module child :
+ | input x : UInt<1>
+ | output z : UInt<1>
+ | z <= not(x)
+ | module Top :
+ | input x : UInt<1>
+ | output z : UInt<1>
+ | inst c of child
+ | inst c_1 of child
+ | c.x <= x
+ | c_1.x <= x
+ | z <= and(c.z, c_1.z)""".stripMargin
+ val check =
+ """circuit Top :
+ | module child :
+ | input x : UInt<1>
+ | output z : UInt<1>
+ | z <= not(x)
+ | module Top :
+ | input x : UInt<1>
+ | output z : UInt<1>
+ | inst c of child
+ | inst c_1 of child
+ | z <= and(c.z, c_1.z)
+ | c.x <= x
+ | c_1.x <= x""".stripMargin
+ val top = CircuitTarget("Top").module("Top")
+ val annos =
+ Seq(top.instOf("c", "child").ref("z"), top.instOf("c_1", "child").ref("z"))
+ .map(DontTouchAnnotation(_))
+ exec(input, check, annos)
+ }
}
class DCECommandLineSpec extends FirrtlFlatSpec {