Merge pull request #1264 from freechipsproject/cleanup-verilog-emitter-casts

Cleanup verilog emitter casts

1 files changed, 24 insertions, 2 deletions

diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index 71709255..af186cda 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -3,8 +3,6 @@
 package firrtlTests
 
 import firrtl._
-import firrtl.ir.Circuit
-import firrtl.Parser.IgnoreInfo
 import firrtl.passes._
 import firrtl.transforms._
 
@@ -824,6 +822,30 @@ class ConstantPropagationSingleModule extends ConstantPropagationSpec {
       """.stripMargin
     (parse(exec(input))) should be(parse(check))
   }
+
+  def castCheck(tpe: String, cast: String): Unit = {
+    val input =
+     s"""circuit Top :
+        |  module Top :
+        |    input  x : $tpe
+        |    output z : $tpe
+        |    z <= $cast(x)
+      """.stripMargin
+    val check =
+     s"""circuit Top :
+        |  module Top :
+        |    input  x : $tpe
+        |    output z : $tpe
+        |    z <= x
+      """.stripMargin
+    (parse(exec(input)).serialize) should be (parse(check).serialize)
+  }
+  it should "optimize unnecessary casts" in {
+    castCheck("UInt<4>", "asUInt")
+    castCheck("SInt<4>", "asSInt")
+    castCheck("Clock", "asClock")
+    castCheck("AsyncReset", "asAsyncReset")
+  }
 }
 
 // More sophisticated tests of the full compiler