Update negative literal emission (#1782)

* test const prop of addition of negative literals

* Emitter: handle minimum negative values correctly

* update expected verilog in AsyncResetSpec

1 files changed, 10 insertions, 0 deletions

diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index 32303949..131f9466 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -1604,4 +1604,14 @@ class ConstantPropagationEquivalenceSpec extends FirrtlFlatSpec {
          |    out <= head_temp""".stripMargin
     firrtlEquivalenceTest(input, transforms)
   }
+
+   "addition of negative literals" should "be propagated" in {
+     val input =
+       s"""circuit AddTester :
+          |  module AddTester :
+          |    output ref : SInt<2>
+          |    ref <= add(SInt<1>("h-1"), SInt<1>("h-1"))
+          |""".stripMargin
+     firrtlEquivalenceTest(input, transforms)
+   }
 }