Revert "Verilog emitter transform InlineNots (#1270)"

This reverts commit f77487d37bd7c61be231a8000a3197d37cf55499.

1 files changed, 0 insertions, 72 deletions

diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index cc7a5e32..18579ca8 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -733,78 +733,6 @@ class ConstantPropagationSingleModule extends ConstantPropagationSpec {
     (parse(exec(input))) should be(parse(check))
   }
 
-   "ConstProp" should "propagate boolean equality with true" in {
-    val input =
-      """circuit Top :
-        |  module Top :
-        |    input x : UInt<1>
-        |    output z : UInt<1>
-        |    z <= eq(x, UInt<1>("h1"))
-      """.stripMargin
-    val check =
-      """circuit Top :
-        |  module Top :
-        |    input x : UInt<1>
-        |    output z : UInt<1>
-        |    z <= x
-      """.stripMargin
-    (parse(exec(input))) should be(parse(check))
-  }
-
-   "ConstProp" should "propagate boolean equality with false" in {
-    val input =
-      """circuit Top :
-        |  module Top :
-        |    input x : UInt<1>
-        |    output z : UInt<1>
-        |    z <= eq(x, UInt<1>("h0"))
-      """.stripMargin
-    val check =
-      """circuit Top :
-        |  module Top :
-        |    input x : UInt<1>
-        |    output z : UInt<1>
-        |    z <= not(x)
-      """.stripMargin
-    (parse(exec(input))) should be(parse(check))
-  }
-
-   "ConstProp" should "propagate boolean non-equality with true" in {
-    val input =
-      """circuit Top :
-        |  module Top :
-        |    input x : UInt<1>
-        |    output z : UInt<1>
-        |    z <= neq(x, UInt<1>("h1"))
-      """.stripMargin
-    val check =
-      """circuit Top :
-        |  module Top :
-        |    input x : UInt<1>
-        |    output z : UInt<1>
-        |    z <= not(x)
-      """.stripMargin
-    (parse(exec(input))) should be(parse(check))
-  }
-
-   "ConstProp" should "propagate boolean non-equality with false" in {
-    val input =
-      """circuit Top :
-        |  module Top :
-        |    input x : UInt<1>
-        |    output z : UInt<1>
-        |    z <= neq(x, UInt<1>("h0"))
-      """.stripMargin
-    val check =
-      """circuit Top :
-        |  module Top :
-        |    input x : UInt<1>
-        |    output z : UInt<1>
-        |    z <= x
-      """.stripMargin
-    (parse(exec(input))) should be(parse(check))
-  }
-
   // Optimizing this mux gives: z <= pad(UInt<2>(0), 4)
   // Thus this checks that we then optimize that pad
   "ConstProp" should "optimize nested Expressions" in {