Merge pull request #617 from freechipsproject/const-prop-regs

Improvements to Constant Propagation and Testing

1 files changed, 74 insertions, 8 deletions

diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index 95785717..f818f9c0 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -2,11 +2,11 @@
 
 package firrtlTests
 
-import org.scalatest.Matchers
+import firrtl._
 import firrtl.ir.Circuit
 import firrtl.Parser.IgnoreInfo
-import firrtl.Parser
 import firrtl.passes._
+import firrtl.transforms._
 
 // Tests the following cases for constant propagation:
 //   1) Unsigned integers are always greater than or
@@ -16,17 +16,17 @@ import firrtl.passes._
 //   3) Values are always greater than a number smaller
 //        than their minimum value
 class ConstantPropagationSpec extends FirrtlFlatSpec {
-  val passes = Seq(
+  val transforms = Seq(
       ToWorkingIR,
       ResolveKinds,
       InferTypes,
       ResolveGenders,
       InferWidths,
-      ConstProp)
-  private def exec (input: String) = {
-    passes.foldLeft(parse(input)) {
-      (c: Circuit, p: Pass) => p.run(c)
-    }.serialize
+      new ConstantPropagation)
+  private def exec(input: String) = {
+    transforms.foldLeft(CircuitState(parse(input), UnknownForm)) {
+      (c: CircuitState, t: Transform) => t.runTransform(c)
+    }.circuit.serialize
   }
    // =============================
    "The rule x >= 0 " should " always be true if x is a UInt" in {
@@ -349,4 +349,70 @@ class ConstantPropagationSpec extends FirrtlFlatSpec {
 """
       (parse(exec(input))) should be (parse(check))
    }
+
+   // =============================
+   "ConstProp" should "work across wires" in {
+      val input =
+"""circuit Top :
+  module Top :
+    input x : UInt<1>
+    output y : UInt<1>
+    wire z : UInt<1>
+    y <= z
+    z <= mux(x, UInt<1>(0), UInt<1>(0))
+"""
+      val check =
+"""circuit Top :
+  module Top :
+    input x : UInt<1>
+    output y : UInt<1>
+    wire z : UInt<1>
+    y <= UInt<1>(0)
+    z <= UInt<1>(0)
+"""
+      (parse(exec(input))) should be (parse(check))
+   }
+}
+
+// More sophisticated tests of the full compiler
+class ConstantPropagationIntegrationSpec extends LowTransformSpec {
+  def transform = new LowFirrtlOptimization
+
+  "ConstProp" should "should not optimize across dontTouch on nodes" in {
+      val input =
+        """circuit Top :
+          |  module Top :
+          |    input x : UInt<1>
+          |    output y : UInt<1>
+          |    node z = x
+          |    y <= z""".stripMargin
+      val check =
+        """circuit Top :
+          |  module Top :
+          |    input x : UInt<1>
+          |    output y : UInt<1>
+          |    node z = x
+          |    y <= z""".stripMargin
+    execute(input, check, Seq(dontTouch("Top.z")))
+  }
+
+  it should "should not optimize across dontTouch on wires" in {
+      val input =
+        """circuit Top :
+          |  module Top :
+          |    input x : UInt<1>
+          |    output y : UInt<1>
+          |    wire z : UInt<1>
+          |    y <= z
+          |    z <= x""".stripMargin
+      val check =
+        """circuit Top :
+          |  module Top :
+          |    input x : UInt<1>
+          |    output y : UInt<1>
+          |    wire z : UInt<1>
+          |    y <= z
+          |    z <= x""".stripMargin
+    execute(input, check, Seq(dontTouch("Top.z")))
+  }
 }