Constant prop add (#849)

* add FoldADD to const prop, add yosys miter tests

* add option for verilog compiler without optimizations

* rename FoldLogicalOp to FoldCommutativeOp

* add GetNamespace and RenameModules, GetNamespace stores namespace as a ModuleNamespaceAnnotation

* add constant propagation for Tail DoPrims

* add scaladocs for MinimumLowFirrtlOptimization and yosysExpectFalure/Success, add constant propagation for Head DoPrim

* add legalize pass to MinimumLowFirrtlOptimizations, use constPropBitExtract in legalize pass

1 files changed, 136 insertions, 0 deletions

diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index 6fc685a8..603ddc25 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -694,6 +694,46 @@ class ConstantPropagationSingleModule extends ConstantPropagationSpec {
 """
       (parse(exec(input))) should be (parse(check))
     }
+
+   "ConstProp" should "propagate constant addition" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    input x : UInt<5>
+        |    output z : UInt<5>
+        |    node _T_1 = add(UInt<5>("h0"), UInt<5>("h1"))
+        |    node _T_2 = add(_T_1, UInt<5>("h2"))
+        |    z <= add(x, _T_2)
+      """.stripMargin
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    input x : UInt<5>
+        |    output z : UInt<5>
+        |    node _T_1 = UInt<6>("h1")
+        |    node _T_2 = UInt<7>("h3")
+        |    z <= add(x, UInt<7>("h3"))
+      """.stripMargin
+    (parse(exec(input))) should be(parse(check))
+  }
+
+   "ConstProp" should "propagate addition with zero" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    input x : UInt<5>
+        |    output z : UInt<5>
+        |    z <= add(x, UInt<5>("h0"))
+      """.stripMargin
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    input x : UInt<5>
+        |    output z : UInt<5>
+        |    z <= pad(x, 6)
+      """.stripMargin
+    (parse(exec(input))) should be(parse(check))
+  }
 }
 
 // More sophisticated tests of the full compiler
@@ -1065,3 +1105,99 @@ class ConstantPropagationIntegrationSpec extends LowTransformSpec {
     execute(input, check, Seq.empty)
   }
 }
+
+
+class ConstantPropagationEquivalenceSpec extends FirrtlFlatSpec {
+  private val srcDir = "/constant_propagation_tests"
+  private val transforms = Seq(new ConstantPropagation)
+
+  "anything added to zero" should "be equal to itself" in {
+    val input =
+      s"""circuit AddZero :
+         |  module AddZero :
+         |    input in : UInt<5>
+         |    output out1 : UInt<6>
+         |    output out2 : UInt<6>
+         |    out1 <= add(in, UInt<5>("h0"))
+         |    out2 <= add(UInt<5>("h0"), in)""".stripMargin
+    firrtlEquivalenceTest(input, transforms)
+  }
+
+  "constants added together" should "be propagated" in {
+    val input =
+      s"""circuit AddLiterals :
+         |  module AddLiterals :
+         |    input uin : UInt<5>
+         |    input sin : SInt<5>
+         |    output uout : UInt<6>
+         |    output sout : SInt<6>
+         |    node uconst = add(UInt<5>("h1"), UInt<5>("h2"))
+         |    uout <= add(uconst, uin)
+         |    node sconst = add(SInt<5>("h1"), SInt<5>("h-1"))
+         |    sout <= add(sconst, sin)""".stripMargin
+    firrtlEquivalenceTest(input, transforms)
+  }
+
+  "UInt addition" should "have the correct widths" in {
+    val input =
+      s"""circuit WidthsAddUInt :
+         |  module WidthsAddUInt :
+         |    input in : UInt<3>
+         |    output out1 : UInt<10>
+         |    output out2 : UInt<10>
+         |    wire temp : UInt<5>
+         |    temp <= add(in, UInt<1>("h0"))
+         |    out1 <= cat(temp, temp)
+         |    node const = add(UInt<4>("h1"), UInt<3>("h2"))
+         |    out2 <= cat(const, const)""".stripMargin
+    firrtlEquivalenceTest(input, transforms)
+  }
+
+  "SInt addition" should "have the correct widths" in {
+    val input =
+      s"""circuit WidthsAddSInt :
+         |  module WidthsAddSInt :
+         |    input in : SInt<3>
+         |    output out1 : UInt<10>
+         |    output out2 : UInt<10>
+         |    wire temp : SInt<5>
+         |    temp <= add(in, SInt<7>("h0"))
+         |    out1 <= cat(temp, temp)
+         |    node const = add(SInt<4>("h1"), SInt<3>("h-2"))
+         |    out2 <= cat(const, const)""".stripMargin
+    firrtlEquivalenceTest(input, transforms)
+  }
+
+  "addition by zero width wires" should "have the correct widths" in {
+    val input =
+      s"""circuit ZeroWidthAdd:
+         |  module ZeroWidthAdd:
+         |    input x: UInt<0>
+         |    output y: UInt<7>
+         |    node temp = add(x, UInt<9>("h0"))
+         |    y <= cat(temp, temp)""".stripMargin
+    firrtlEquivalenceTest(input, transforms)
+  }
+
+  "tail of constants" should "be propagated" in {
+    val input =
+      s"""circuit TailTester :
+         |  module TailTester :
+         |    output out : UInt<1>
+         |    node temp = add(UInt<1>("h00"), UInt<5>("h017"))
+         |    node tail_temp = tail(temp, 1)
+         |    out <= tail_temp""".stripMargin
+    firrtlEquivalenceTest(input, transforms)
+  }
+
+  "head of constants" should "be propagated" in {
+    val input =
+      s"""circuit TailTester :
+         |  module TailTester :
+         |    output out : UInt<1>
+         |    node temp = add(UInt<1>("h00"), UInt<5>("h017"))
+         |    node head_temp = head(temp, 3)
+         |    out <= head_temp""".stripMargin
+    firrtlEquivalenceTest(input, transforms)
+  }
+}