Asynchronous Reset (#1011)

Fixes #219

* Adds AsyncResetType (similar to ClockType)
* Registers with reset signal of type AsyncResetType are async reset
  registers
* Registers with async reset can only be reset to literal values
* Add initialization logic for async reset registers

1 files changed, 26 insertions, 0 deletions

diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index ee2540e0..6fb2ab8d 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -1005,6 +1005,32 @@ class ConstantPropagationIntegrationSpec extends LowTransformSpec {
     execute(input, check, Seq.empty)
   }
 
+  "Registers async reset and a constant connection" should "NOT be removed" in {
+      val input =
+        """circuit Top :
+          |  module Top :
+          |    input clock : Clock
+          |    input reset : AsyncReset
+          |    input en : UInt<1>
+          |    output z : UInt<8>
+          |    reg r : UInt<8>, clock with : (reset => (reset, UInt<4>("hb")))
+          |    when en :
+          |      r <= UInt<4>("h0")
+          |    z <= r""".stripMargin
+      val check =
+        """circuit Top :
+          |  module Top :
+          |    input clock : Clock
+          |    input reset : AsyncReset
+          |    input en : UInt<1>
+          |    output z : UInt<8>
+          |    reg r : UInt<8>, clock with :
+          |      reset => (reset, UInt<8>("hb"))
+          |    z <= r
+          |    r <= mux(en, UInt<8>("h0"), r)""".stripMargin
+    execute(input, check, Seq.empty)
+  }
+
   "Registers with constant reset and connection to the same constant" should "be replaced with that constant" in {
       val input =
         """circuit Top :