Clk2clock - rename the implicit "clk" module input "clock" (#387)

* Rename implict module "clk" input to "clock".
This doesn't rename all the "self-contained" test instances.
nor the memory "clk" enables,
nor the implict module "clk"s in the regress .fir files.

* Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances.
This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.

1 files changed, 4 insertions, 4 deletions

diff --git a/src/test/scala/firrtlTests/ChirrtlSpec.scala b/src/test/scala/firrtlTests/ChirrtlSpec.scala
index 3b360de6..0ae112f0 100644
--- a/src/test/scala/firrtlTests/ChirrtlSpec.scala
+++ b/src/test/scala/firrtlTests/ChirrtlSpec.scala
@@ -35,9 +35,9 @@ class ChirrtlSpec extends FirrtlFlatSpec {
     val input =
      """circuit Unit :
        |  module Unit :
-       |    input clk : Clock
+       |    input clock : Clock
        |    smem ram : UInt<32>[128]
-       |    node newClock = clk
+       |    node newClock = clock
        |    infer mport x = ram[UInt(2)], newClock
        |    x <= UInt(3)
        |    when UInt(1) :
@@ -53,9 +53,9 @@ class ChirrtlSpec extends FirrtlFlatSpec {
     val input =
      """circuit Unit :
        |  module Unit :
-       |    input clk : Clock
+       |    input clock : Clock
        |    smem ram : UInt<32>[128]
-       |    node newClock = clk
+       |    node newClock = clock
        |    infer mport x = ram[UInt(2)], newClock
        |    x <= UInt(3)
        |    when UInt(1) :