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authorAdam Izraelevitz2017-05-10 11:23:18 -0700
committerGitHub2017-05-10 11:23:18 -0700
commit8b8eb4eac5b353d4d632065c78faf6a706d6aae8 (patch)
tree39e2d9344166b61b376df9d3cd15a4787bcd01f4 /src/test/scala/firrtlTests/ChirrtlSpec.scala
parentaf222c1737fa72fce964190876346bdb7ff220cd (diff)
Update rename2 (#478)
* Added pass name to debug logger * Addresses #459. Rewords transform annotations API. Now, any annotation not propagated by a transform is considered deleted. A new DeletedAnnotation is added in place of it. * Added more stylized debugging style * WIP: make pass transform * WIP: All tests pass, need to pull master * Cleaned up PR * Added rename updates to all core transforms * Added more rename tests, and bugfixes * Renaming tracks non-leaf subfields E.g. given: wire x: {a: UInt<1>, b: UInt<1>[2]} Annotating x.b will eventually annotate x_b_0 and x_b_1 * Bugfix instance rename lowering broken * Address review comments * Remove check for seqTransform, UnknownForm too restrictive check
Diffstat (limited to 'src/test/scala/firrtlTests/ChirrtlSpec.scala')
-rw-r--r--src/test/scala/firrtlTests/ChirrtlSpec.scala13
1 files changed, 8 insertions, 5 deletions
diff --git a/src/test/scala/firrtlTests/ChirrtlSpec.scala b/src/test/scala/firrtlTests/ChirrtlSpec.scala
index 0ae112f0..fd4374f0 100644
--- a/src/test/scala/firrtlTests/ChirrtlSpec.scala
+++ b/src/test/scala/firrtlTests/ChirrtlSpec.scala
@@ -8,9 +8,10 @@ import org.scalatest.prop._
import firrtl.Parser
import firrtl.ir.Circuit
import firrtl.passes._
+import firrtl._
class ChirrtlSpec extends FirrtlFlatSpec {
- def passes = Seq(
+ def transforms = Seq(
CheckChirrtl,
CInferTypes,
CInferMDir,
@@ -44,8 +45,9 @@ class ChirrtlSpec extends FirrtlFlatSpec {
| infer mport y = ram[UInt(4)], newClock
| y <= UInt(5)
""".stripMargin
- passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
- (c: Circuit, p: Pass) => p.run(c)
+ val circuit = Parser.parse(input.split("\n").toIterator)
+ transforms.foldLeft(CircuitState(circuit, UnknownForm)) {
+ (c: CircuitState, p: Transform) => p.runTransform(c)
}
}
@@ -63,8 +65,9 @@ class ChirrtlSpec extends FirrtlFlatSpec {
| y <= z
""".stripMargin
intercept[PassException] {
- passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
- (c: Circuit, p: Pass) => p.run(c)
+ val circuit = Parser.parse(input.split("\n").toIterator)
+ transforms.foldLeft(CircuitState(circuit, UnknownForm)) {
+ (c: CircuitState, p: Transform) => p.runTransform(c)
}
}
}