diff options
| author | Albert Magyar | 2019-08-07 15:13:57 -0700 |
|---|---|---|
| committer | mergify[bot] | 2019-08-07 22:13:57 +0000 |
| commit | 23a104d3409385718a960427f1576f508e3f473b (patch) | |
| tree | 1bde53f80a0fe0f0c32eb0a1432f413989fd75b4 /src/test/scala/firrtlTests/ChirrtlSpec.scala | |
| parent | 0fe6aad23a4aee50119b9fe2645ba2ff833f65bb (diff) | |
DRY check chirrtl (#1148)
* Avoid redundancy between CheckChirrtl and CheckHighForm, add more checks
* Add test case for illegal Chirrtl memory in HighForm
Diffstat (limited to 'src/test/scala/firrtlTests/ChirrtlSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/ChirrtlSpec.scala | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/src/test/scala/firrtlTests/ChirrtlSpec.scala b/src/test/scala/firrtlTests/ChirrtlSpec.scala index 9344b861..aeb70c8d 100644 --- a/src/test/scala/firrtlTests/ChirrtlSpec.scala +++ b/src/test/scala/firrtlTests/ChirrtlSpec.scala @@ -2,13 +2,8 @@ package firrtlTests -import java.io._ -import org.scalatest._ -import org.scalatest.prop._ -import firrtl.{Parser, CircuitState, UnknownForm, Transform} -import firrtl.ir.Circuit -import firrtl.passes._ import firrtl._ +import firrtl.passes._ class ChirrtlSpec extends FirrtlFlatSpec { def transforms = Seq( |