diff options
| author | jackkoenig | 2016-05-11 23:44:14 -0700 |
|---|---|---|
| committer | jackkoenig | 2016-05-12 00:15:40 -0700 |
| commit | 0ee659e85c7fe46c2678a49866ef1eca8f4a2c65 (patch) | |
| tree | a78810b137d106a59b56d9d38e985796ea8da97f /src/test/scala/firrtlTests/ChirrtlSpec.scala | |
| parent | 6d72dfbb50a9ccd7944b90d509d9796704aa69a9 (diff) | |
Implement File Info
Diffstat (limited to 'src/test/scala/firrtlTests/ChirrtlSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/ChirrtlSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/ChirrtlSpec.scala b/src/test/scala/firrtlTests/ChirrtlSpec.scala index dd2b7e31..0059d7ed 100644 --- a/src/test/scala/firrtlTests/ChirrtlSpec.scala +++ b/src/test/scala/firrtlTests/ChirrtlSpec.scala @@ -67,7 +67,7 @@ class ChirrtlSpec extends FirrtlFlatSpec { | infer mport y = ram[UInt(4)], newClock | y <= UInt(5) """.stripMargin - passes.foldLeft(Parser.parse("",input.split("\n").toIterator)) { + passes.foldLeft(Parser.parse(input.split("\n").toIterator)) { (c: Circuit, p: Pass) => p.run(c) } } |
