diff options
| author | Jack Koenig | 2017-06-28 17:52:56 -0700 |
|---|---|---|
| committer | Jack Koenig | 2017-06-28 17:52:56 -0700 |
| commit | 39665e1f74cfe8243067442cccf4e7eab66ade68 (patch) | |
| tree | 8ba403e298c39bc6104f32a93754079dc458752a /src/test/scala/firrtlTests/ChirrtlMemSpec.scala | |
| parent | 818cfde4ad42ffa9ee30d0f9ae72533ede80e4ce (diff) | |
Promote ConstProp to a transform
Diffstat (limited to 'src/test/scala/firrtlTests/ChirrtlMemSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/ChirrtlMemSpec.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/ChirrtlMemSpec.scala b/src/test/scala/firrtlTests/ChirrtlMemSpec.scala index c963c8ae..6fac5047 100644 --- a/src/test/scala/firrtlTests/ChirrtlMemSpec.scala +++ b/src/test/scala/firrtlTests/ChirrtlMemSpec.scala @@ -5,6 +5,7 @@ package firrtlTests import firrtl._ import firrtl.ir._ import firrtl.passes._ +import firrtl.transforms._ import firrtl.Mappers._ import annotations._ @@ -53,7 +54,7 @@ class ChirrtlMemSpec extends LowTransformSpec { def transform = new SeqTransform { def inputForm = LowForm def outputForm = LowForm - def transforms = Seq(ConstProp, MemEnableCheckPass) + def transforms = Seq(new ConstantPropagation, MemEnableCheckPass) } "Sequential Memory" should "have correct enable signals" in { |
