diff options
| author | Schuyler Eldridge | 2019-09-16 19:03:37 -0400 |
|---|---|---|
| committer | GitHub | 2019-09-16 19:03:37 -0400 |
| commit | f93e1d240f80848dc12c25906239fe6c8a4d42b5 (patch) | |
| tree | 9b39634fc4bd5044e37939a0bd568ae4ed158826 /src/test/scala/firrtlTests/CheckSpec.scala | |
| parent | 7e39ea8ec948ff1db7ccd0d850923a86d2d8a4e7 (diff) | |
| parent | b3dd7924f27342083681be6dd5932ef95d354029 (diff) | |
Merge pull request #1124 from freechipsproject/gender-to-flow
Gender to Flow
Diffstat (limited to 'src/test/scala/firrtlTests/CheckSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/CheckSpec.scala | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala index 54dc60ab..96275003 100644 --- a/src/test/scala/firrtlTests/CheckSpec.scala +++ b/src/test/scala/firrtlTests/CheckSpec.scala @@ -5,7 +5,7 @@ package firrtlTests import org.scalatest._ import firrtl.{Parser, CircuitState, UnknownForm, Transform} import firrtl.ir.Circuit -import firrtl.passes.{Pass,ToWorkingIR,CheckHighForm,ResolveKinds,InferTypes,CheckTypes,PassException,InferWidths,CheckWidths,ResolveGenders,CheckGenders} +import firrtl.passes.{Pass,ToWorkingIR,CheckHighForm,ResolveKinds,InferTypes,CheckTypes,PassException,InferWidths,CheckWidths,ResolveFlows,CheckFlows} class CheckSpec extends FlatSpec with Matchers { val defaultPasses = Seq(ToWorkingIR, CheckHighForm) @@ -176,8 +176,8 @@ class CheckSpec extends FlatSpec with Matchers { ResolveKinds, InferTypes, CheckTypes, - ResolveGenders, - CheckGenders, + ResolveFlows, + CheckFlows, new InferWidths, CheckWidths) val input = |
