Merge pull request #1852 from freechipsproject/format-src-4

Apply Scalafmt Rewriting

1 files changed, 26 insertions, 26 deletions

diff --git a/src/test/scala/firrtlTests/CheckInitializationSpec.scala b/src/test/scala/firrtlTests/CheckInitializationSpec.scala
index 34e0da03..5fd9543e 100644
--- a/src/test/scala/firrtlTests/CheckInitializationSpec.scala
+++ b/src/test/scala/firrtlTests/CheckInitializationSpec.scala
@@ -2,27 +2,27 @@
 
 package firrtlTests
 
-import firrtl.{CircuitState, UnknownForm, Transform}
+import firrtl.{CircuitState, Transform, UnknownForm}
 import firrtl.passes._
 import firrtl.testutils._
 
 class CheckInitializationSpec extends FirrtlFlatSpec {
   private val passes = Seq(
-     ToWorkingIR,
-     CheckHighForm,
-     ResolveKinds,
-     InferTypes,
-     CheckTypes,
-     ResolveFlows,
-     CheckFlows,
-     new InferWidths,
-     CheckWidths,
-     PullMuxes,
-     ExpandConnects,
-     RemoveAccesses,
-     ExpandWhens,
-     CheckInitialization,
-     InferTypes
+    ToWorkingIR,
+    CheckHighForm,
+    ResolveKinds,
+    InferTypes,
+    CheckTypes,
+    ResolveFlows,
+    CheckFlows,
+    new InferWidths,
+    CheckWidths,
+    PullMuxes,
+    ExpandConnects,
+    RemoveAccesses,
+    ExpandWhens,
+    CheckInitialization,
+    InferTypes
   )
   "Missing assignment in consequence branch" should "trigger a PassException" in {
     val input =
@@ -33,8 +33,8 @@ class CheckInitializationSpec extends FirrtlFlatSpec {
         |    when p :
         |      x <= UInt(1)""".stripMargin
     intercept[CheckInitialization.RefNotInitializedException] {
-      passes.foldLeft(CircuitState(parse(input), UnknownForm)) {
-        (c: CircuitState, p: Transform) => p.runTransform(c)
+      passes.foldLeft(CircuitState(parse(input), UnknownForm)) { (c: CircuitState, p: Transform) =>
+        p.runTransform(c)
       }
     }
   }
@@ -48,8 +48,8 @@ class CheckInitializationSpec extends FirrtlFlatSpec {
         |    else :
         |      x <= UInt(1)""".stripMargin
     intercept[CheckInitialization.RefNotInitializedException] {
-      passes.foldLeft(CircuitState(parse(input), UnknownForm)) {
-        (c: CircuitState, p: Transform) => p.runTransform(c)
+      passes.foldLeft(CircuitState(parse(input), UnknownForm)) { (c: CircuitState, p: Transform) =>
+        p.runTransform(c)
       }
     }
   }
@@ -64,8 +64,8 @@ class CheckInitializationSpec extends FirrtlFlatSpec {
         |      x <= UInt(1)
         |    x <= UInt(1)
         |    """.stripMargin
-    passes.foldLeft(CircuitState(parse(input), UnknownForm)) {
-      (c: CircuitState, p: Transform) => p.runTransform(c)
+    passes.foldLeft(CircuitState(parse(input), UnknownForm)) { (c: CircuitState, p: Transform) =>
+      p.runTransform(c)
     }
   }
 
@@ -84,8 +84,8 @@ class CheckInitializationSpec extends FirrtlFlatSpec {
         |        x <= UInt(2)
         |    x <= UInt(1)
         |    """.stripMargin
-    passes.foldLeft(CircuitState(parse(input), UnknownForm)) {
-      (c: CircuitState, p: Transform) => p.runTransform(c)
+    passes.foldLeft(CircuitState(parse(input), UnknownForm)) { (c: CircuitState, p: Transform) =>
+      p.runTransform(c)
     }
   }
 
@@ -100,8 +100,8 @@ class CheckInitializationSpec extends FirrtlFlatSpec {
         |    when p :
         |      c.in <= UInt(1)""".stripMargin
     intercept[CheckInitialization.RefNotInitializedException] {
-      passes.foldLeft(CircuitState(parse(input), UnknownForm)) {
-        (c: CircuitState, p: Transform) => p.runTransform(c)
+      passes.foldLeft(CircuitState(parse(input), UnknownForm)) { (c: CircuitState, p: Transform) =>
+        p.runTransform(c)
       }
     }
   }